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document number: mc33742 rev. 10.0, 5/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. system basis chip (sbc) with enhanced high-speed can transceiver the 33742 and the 33742s are spi-con trolled system basis chips (sbcs) combining many frequently us ed functions along with a can 2.0- compliant transceiver, used in many automotive electron ic control units (ecus). the 33742 sbc has a fully protected fixed 5.0 v low dropout internal regulator with current limitin g, overtemperature pre-warning, and reset. a second 5.0 v regulator can be implemented using external pass pnp bipolar junction pass transistor driven by the sbc?s external v2 sense input and v2 output drive pins. the sbc has four main operating modes: normal, standby, stop, and sleep mode. additionally there is an internally switched high-side power supply output, four wake-up inpu ts pins, a programmable window watchdog, interrupt, reset, and a spi module for communication and control. the high-speed can a and b transceiver is available for inter- module communication. features ?1.0 mbps can transceiver bus interface with bus diagnostic capability ? spi control at frequencies up to 4.0 mhz ? 5.0 v low dropout voltage regulator with current limiting, overtemperature pre-warning, and output monitoring and reset ? a second 5.0 v regulator capability using an external series pass transistor ? normal, standby, stop, and sleep modes of operation with low sleep and stop mode current ? a high-side (hs) switch output driver for controlling external circuitry. ? pb-free packaging designated by suffix code eg and ep figure 1. 33742 simplified application diagram system basis chip 33742 33742s ordering information device temperature range (t a ) package mc33742dw/r2 - 40c to 125c 28 soicw MCZ33742eg/r2 mc33742sdw/r2 MCZ33742seg/r2 pcz33742ep/r2 48 qfn dw suffix eg suffix (pb-free) 98asb42345b 28-pin soicw ep suffix (pb-free) 98arh99048a 48-pin qfn 5.0 v mcu gnd vsup 33742 gnd vdd rst v2 v2ctrl hs wdog v pwr v pwr v 2 safe circuitry sclk mosi miso cs spi sclk mosi miso cs int txd rxd canh canl tw isted pair l1 l2 l3 l0 ecu local supply can bus
analog integrated circuit device data 2 freescale semiconductor 33742 device variations device variations table 1. device differences during a reset condition part no. reset duration device differences see page 33742 15 ms (typical) the duration the rst pin is asserted low when the reset mode is entered after the sbc is powered up and a v dd undervoltage condition is detected and the watchdog register is not properly triggered. page 19 33742s 3.5 ms (typical) the duration the rst pin is asserted low when the reset mode is entered after the sbc is powered up and a v dd undervoltage condition is detected and the watchdog register is not properly triggered. page 19
analog integrated circuit device data freescale semiconductor 3 33742 internal block diagram internal block diagram figure 2. 33742 simplifi ed internal block diagram spi high-speed 1.0 mbps can physical interface sclk mosi gnd programmable wake-up input vsup txd rxd l1 hs interrupt watchdog reset miso cs rst wdog int oscillator mode control hs control vsup monitor dual voltage regulator l2 l3 l4 5.0 v / 200 ma v1 v2ctrl v2 canh canl v1 monitor
analog integrated circuit device data 4 freescale semiconductor 33742 pin connections pin connections figure 3. 33742 28-pin connections wdog miso sclk gnd gnd gnd gnd canl canh l3 l2 l1 cs mosi rxd rst int gnd gnd gnd gnd v2 v2ctrl vsup hs l0 txd vdd 4 5 6 7 8 9 10 11 12 13 14 2 3 28 25 24 23 22 21 20 19 18 17 16 15 27 26 1 table 2. 33742 28-pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 22 . pin pin name formal name definition 1 rxd receive data can bus receive data output pin. 2 txd transmit data can bus transmit data input pin. 3 vdd voltage digital drain 5.0 v regulator output pin. supply pin for the mcu. 4 rst reset output (active low) this is the device reset output pin whose main function is to reset the mcu. this pin has an internal pullup current source to vdd. 5 int interrupt output (active low) this output is asserted low when an enabled interrupt condition occurs. the output is a push-pull structure. 6 ? 9 20 ? 23 gnd ground these device ground pins are internally c onnected to the package lead frame to provide a 33742-to-pcb thermal path. 10 v2 voltage source 2 sense input for the v2 regulator using an extern al series pass transistor. v2 is also the internal supply for the can transceiver. 11 v2ctrl voltage source 2 control output drive source for the v2 regulator con nected to the external series pass transistor. 12 vsup voltage supply supply input pin for the 33742. 13 hs high-side output output of the internal high-side switch. the output current is internally limited to 150 ma. 14 ?17 l0- l3 level 0 - 3 inputs inputs from external switches or from logic circuitry. 18 canh can high output can high output pin. 19 canl can low output can low output pin. 24 sclk serial data clock clock input pin for the serial peripheral interface (spi). 25 miso master in slave out spi data sent to the mcu by the 33742. when cs is high, the pin is in the high- impedance state. 26 mosi master out slave in spi data received by the 33742. 27 cs chip select (active low) the cs input pin is used with the spi bus to select the 33742. when the cs is asserted low, the 33742 is the selected device of the spi bus. 28 wdog watchdog output (active low) the wdog output pin is asserted low if the software watchdog is not correctly triggered.
analog integrated circuit device data freescale semiconductor 5 33742 pin connections figure 4. 33742 48-pin connections table 3. 33742 48-pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 22 . pin pin name formal name definition 1, 12-16, 21-25, 36-40, 45-48 nc no connect no connection. 2 sclk serial data clock clock input pin for the serial peripheral interface (spi). 3 miso master in slave out spi data sent to the mcu by the 33742. when cs is high, the pin is in the high- impedance state. 4 mosi master out slave in spi data received by the 33742. 5 cs chip select (active low) the cs input pin is used with the spi bus to select the 33742. when the cs is asserted low, the 33742 is the selected device of the spi bus. 6 wdog watchdog output (active low) the wdog output pin is asserted low if the software watchdog is not correctly triggered. 7 rxd receive data can bus receive data output pin. 8 txd transmit data can bus transmit data input pin. 9 vdd voltage digital drain 5.0 v regulator output pin. supply pin for the mcu. 10 rst reset output (active low) this is the device reset output pin whose main function is to reset the mcu. this pin has an internal pullup current source to vdd. 11 int interrupt output (active low) this output is asserted low when an enabled in terrupt condition occurs. the output is a push-pull structure. 17-20 41-44 gnd ground these device ground pins are internally c onnected to the package lead frame to provide a 33742-to-pcb thermal path. gnd gnd gnd sclk 4 5 6 7 8 9 10 11 12 2 3 32 29 28 27 26 31 30 1 14 15 16 36 35 rxd 17 18 34 33 38 39 40 41 42 43 19 20 22 23 24 44 45 46 47 48 gnd 25 l3 l2 l1 l0 nc nc nc vdd txd 13 37 v2 ctrl canh canl nc nc nc nc nc nc miso mosi wdog int nc gnd gnd nc nc nc gnd nc nc nc hs vsup cs rst nc nc nc v2 gnd nc 21
analog integrated circuit device data 6 freescale semiconductor 33742 pin connections 26 v2 voltage source 2 sense input for the v2 regulator using an exter nal series pass transistor. v2 is also the internal supply for the can transceiver. 27 v2ctrl voltage source 2 control output drive source for the v2 regulator connected to the external series pass transistor. 28 vsup voltage supply supply input pin for the 33742. 29 hs high-side output output of the internal high-side switch. the output current is internally limited to 150 ma. 30-33 l0- l3 level 0 - 3 inputs inputs from external switc hes or from logic circuitry. 34 canh can high output can high output pin. 35 canl can low output can low output pin. table 3. 33742 48-pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 22 . pin pin name formal name definition
analog integrated circuit device data freescale semiconductor 7 33742 electrical characteristics maximum ratings electrical characteristics maximum ratings table 4. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit electrical ratings power supply voltage at vsup continuous (steady-state) transient voltage (load dump) v sup - 0.3 to 27 - 0.3 to 40 v logic signals (rxd, txd, mosi, miso, cs , sclk, rst , wdog , and int ) v log - 0.3 to v dd + 0.3 v output voltage at vdd v dd 0.0 to 5.3 v output current at vdd i dd internally limited a hs voltage output current v hs i hs - 0.3 to v sup + 0.3 internally limited v a esd capability, human body model (1) hs, l0, l1, l2, l3, canh, canl pins all other pins v esd1 4000 2000 v esd capability, machine model (1) v esd2 200 v input voltage/current at l0, l1, l2, l3 dc input voltage dc input current transient input voltage attached to external circuitry (2) v dcin i dcin v trinec - 0.3 to 40 2.0 100 v ma v canl and canh continuous voltage continuous current v canh/l i canh/l - 27 to 40 200 v ma canh and canl transient voltage (load dump) (3) v ldh/l 40 v canh and canl transient voltage (3) v trh/l 40 v notes 1. testing done in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), machine model (c zap = 200 pf, r zap = 0 ? ). 2. testing done in accordance with iso 7637-1. see figure 5 . 3. load dump testing done in accordance with iso 7637-1, transient test done in accordance with iso 7637-1. see figure 6 .
analog integrated circuit device data 8 freescale semiconductor 33742 electrical characteristics maximum ratings figure 5. transient test setup for l0 : l3 inputs figure 6. transient test setup for canh / canl thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c storage temperature t stg - 55 to 165 c thermal resistance r jg 20 c/w thermal resistance junction case (qfn) r tjc -r jc tbd c/w power dissipation (4) p d 1.0 w peak package reflow temperature during reflow (6) , (7) t pprt note 7 c notes 4. maximum power dissipation is at 85c am bient temperature in free air and with no heatsink, according to jedec jesd51-2 and jesd51-3 specifications. 5. the package is not designed for imme rsion soldering. the maximum soldering time is 10 seconds at 240 c on any pin. exceeding the maximum temperature and time limits may cause permanent damage to the device. 6. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersio n soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 7. freescale?s package reflow capability meets pb-free requirem ents for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. table 4. maximum ratings (continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit l x transient pulse gnd generator 1.0 nf (note) 10 k ? note waveform per iso 7637-1. test pulses 1, 2, 3a, and 3b. gnd 33742 canh canl transient pulse gnd gnd generator 1.0 nf 1.0 nf (note) note waveform per iso 7637-1. test pulses 1, 2, 3a, and 3b. 33742
analog integrated circuit device data freescale semiconductor 9 33742 electrical characteristics static electrical characteristics static electrical characteristics table 5. static electrical characteristics characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit input pin (vsup) supply voltage nominal dc voltage extended dc voltage: full functionality (8) extended dc voltage: reduced functionality (9) load dump jump start v sup 5.5 18 4.5 ? ? ? ? ? ? ? 18 27 5.5 40 27 v supply current in standby mode (10) (i out at vdd = 40 ma, can recessive or sleep mode) t a 25 c i sup(stdby) ? 42 45 ma supply current in normal mode (10) (i out at vdd = 40 ma, can recessive or sleep mode) t a 25 c i sup(norm) ? 42 45 ma supply current in sleep mode (10) (vdd and v2 off, can in sleep mode with can wake-up disabled (11) ) v sup < 13.5 v, oscillator running (12) v sup < 13.5 v, oscillator not running (13) v sup = 18 v, oscillator running (12) i sup(slp-wd) ? ? ? 85 53 110 105 80 140 a supply current in sleep mode (10) (v1 and v2 off, v sup < 13.5 v, oscillator not running (13) , can in sleep mode with wake-up enabled) t a = - 40 c t a = 25 c t a = 125 c i sup(slp-we) ? ? ? 80 65 55 ? ? ? a supply current in stop mode (10) (i out at vdd < 2.0 ma, vdd on, can in sleep mode with wake-up disabled (11) ) vsup < 13.5 v, oscillator running (12) vsup < 13.5 v, oscillator not running (13) vsup = 18 v, oscillator running (12) i sup(stop-wd) ? ? ? ? 80 100 160 160 210 a notes 8. all functions and modes available and operating: watchdog, hs turn on / turn off, can transceiver operating, l0 : l3 inputs operating, normal spi operation. the 33742 may experience an over temperature fault. 9. at vdd > 4.0 v, rst high if reset 2 selected via spi. the logic high level will be degraded but the 33742 is functional. 10. current measured at vsup pin. 11. if can module is sleep-enabled for wake-up, an additional current (i can-sleep ) must be added to specified value. 12. oscillator running means one of the follo wing function is active: forced wake-up or cyclic sense or software watchdog in stop mode. 13. oscillator not running means none of the foll owing functions are active: forced wake-up and cyclic sense and software watchdog in stop mode.
analog integrated circuit device data 10 freescale semiconductor 33742 electrical characteristics static electrical characteristics input pin (vsup) (continued) supply current in stop mode (14) ( i out at vdd < 2.0 ma, vdd on, vsup < 13.5 v, oscillator not running, can in sleep mode with wake-up enabled) (15) t a = - 40 c t a = 25 c t a = 125 c i sup(stop-we) ? ? ? 100 92 80 ? ? ? a batfail flag internal threshold v bf 1.5 3.0 4.0 v batfail flag hysteresis (16) v bf(hys) ? 1.0 ? v battery fall early warning threshold in normal and standby modes v bf(ew) 5.3 5.8 6.3 v battery fall early warning hysteresis in normal and standby modes (16) v bf(ew-hyst) 0.1 0.2 0.3 v output pin (vdd) (17) vdd output voltage (2.0 ma < i v1 < 200 ma) 5.5 v < vsup < 27 v 4.5 v < vsup < 5.5 v v ddout 4.9 4.0 5.0 ? 5.1 ? v dropout voltage i dd = 200 ma v dddrp1 ? 0.2 0.5 v dropout voltage, limited output current and low v sup i dd = 50 ma, 4.5 v < vsup v dddrp2 ? 0.1 0.25 v output current internally limited i dd 200 285 350 ma thermal shutdown (junction) normal or standby mode t sd 160 ? 200 c overtemperature pre-warning (junction) vddtemp bit set t pw 125 ? 160 c notes 14. current measured at vsup pin. 15. oscillator not running means none of the foll owing functions are active: forced wake-up and cyclic sense and software watchdog in stop mode. 16. guaranteed by design; it is not production tested. 17. i dd is the total regulator output current. v1 specification wi th external capacitor. stabilit y requirement: capacitance > 47 f, esr < 1.3 ? (tantalum capacitor). in reset, normal request, normal and standby modes. measures with capacitance = 47 f tantalum. table 5. static electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33742 electrical characteristics static electrical characteristics output pin (vdd) (continued) (18) temperature threshold difference t sd - t pw 20 ? 40 c reset threshold threshold 1, default value after reset, rstth bit set to logic [0] threshold 2, rstth bit set to logic [1] v rst th 4.5 4.0 4.6 4.2 4.7 4.3 v vdd for reset active v ddr 1.0 ? v rst th v line regulation (i dd = 10 ma, capacitance = 47 f tantalum at vdd) 9.0 v < v sup < 18 v 5.5 v < v sup < 27 v v ddr ? ? 5.0 10 25 25 mv load regulation (capacitance = 47 f tantalum at v1) 1.0 ma < i dd < 200 ma v ld ? 25 75 mv thermal stability v sup = 13.5 v, i dd = 100 ma (19) v therm-s ? 30 50 mv output pin in stop mode (vdd) (18) vdd output voltage i dd 2.0 ma i dd 10 ma v ddstop 4.75 4.75 5.0 5.0 5.25 5.25 v i dd output current to wake-up i dds-wu 10 17 25 ma reset threshold (18) threshold 1, default value after reset, rstth bit set to logic [0] threshold 2, rstth bit set to logic [1] v rst -stop 4.5 4.1 4.6 4.2 4.7 4.3 v line regulation (capacitance = 47 f tantalum at vdd) 5.5 v < v sup < 27 v, i dd = 2.0 ma v lr-stop ? 5.0 25 mv load regulation (capacitance = 47 f tantalum at v1) 1.0 ma < i dd < 10 ma v ld-stop ? 15 75 mv notes 18. i dd is the total regulator output current. vdd specification wi th external capacitor. stabili ty requirement: capacitance > 47 f, esr < 1.3 ? (tantalum capacitor). in reset, normal request, norm al and standby modes, measures with capacitance = 47 f tantalum.selectable by rstth bit in spi register reset control register (rcr). 19. guaranteed by characterization and des ign; it is not production tested. table 5. static electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33742 electrical characteristics static electrical characteristics tracking voltage regulator (v2) (20) v2 output voltage (capacitance = 10 f tantalum at v2) 2.0 ma i v2 200 ma, 5.5 v < v sup < 27 v v 2 0.99 1.0 1.01 v dd i v2 output current (for information only) depending on external ballast transistor i v2 200 ? ? ma v2 control drive current capability (21) worst case at t j = 125c i v2ctrl 0.0 ? 10 ma v2low flag threshold v 2lth 3.75 4.0 4.25 v logic output pin (miso) (22) low-level output voltage i out = 1.5 ma v ol 0.0 ? 1.0 v high-level output voltage i out = -250 a v oh v dd - 0.9 ? v dd v tri-stated miso leakage current 0 v < v miso < v dd i hz - 2.0 ? 2.0 a notes 20. v2 specification with external capacit or. stability requirement: capacitance > 42 f and esr < 1.3 ? (tantalum capacitor), external resistor between base and emitter required. measurement c onditions: ballast transistor mjd32c, capacitance > 10 f tantalum, 2.2 k ? resistor between base and emi tter of ballast transistor. 21. the guaranteed v2ctrl current capability is 10 ma. no active current limiting is used so the actual available current may be higher. 22. push-pull structure with tri-state condition ( cs high). table 5. static electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 33742 electrical characteristics static electrical characteristics logic input pins (mosi, sclk, cs ) high-level input voltage v ih 0.7 v dd ? v dd + 0.3 v low-level input voltage v il - 0.3 ? 0.3 v dd v high-level input current on cs v in = 4.0 v i ih -100 ? - 20 a low-level input current on cs v in = 1.0 v i il -100 ? - 20 a mosi and sclk input current 0 v < v in < v dd i in -10 ? 10 a output pin ( rst ) (23) high-level output current 0 v < v out < 0.7 v dd i oh - 300 - 250 -150 a low-level output voltage i o = 1.5 ma, 5.5 v < v sup < 27 v i o = 0 ma, 1.0 v 0.9 v i pdw 2.3 ? 5.0 ma output pin ( wdog ) (24) low-level output voltage i o = 1.5 ma, 1.0 v < v sup < 27 v v ol 0.0 ? 0.9 v high-level output voltage i o = -250 a v oh v dd - 0.9 ? v dd v output pin ( int ) (24) low-level output voltage i o = 1.5 ma v ol 0.0 ? 0.9 v high-level output voltage i o = -250 a v oh v dd - 0.9 ? v dd v notes 23. output pin only. supply from vdd. structur e switch to ground with pullup current source. 24. push-pull structure. table 5. static electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 33742 electrical characteristics static electrical characteristics output pin (hs) driver output on resistance t a = 25c, i out - 150 ma, v sup > 9.0 v t a = 125c, i out - 150 ma, v sup > 9.0 v t a = 125c, i out - 120 ma, 5.5 v < v sup < 9.0 v r ds(on) ? ? ? 2.0 ? 3.5 2.5 4.5 5.5 ? output current limitation v sup - v hs > 1.0 v i lim 160 ? 500 ma hs thermal shutdown t sd 155 ? 190 c hs leakage current i leak ? ? 10 a output clamp voltage i out = -10 ma, no inductive load drive capability v cl -1.5 ? - 0.3 v input pins (l0, l1, l2, and l3) low-voltage detection threshold 5.5 v < v sup < 6.0 v 6.0 v < v sup < 18 v 18 v < v sup < 27 v v thl 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.6 3.7 v high-voltage detection threshold 5.5 v < v sup < 6.0 v 6.0 v < v sup < 18 v 18 v < v sup < 27 v v thh 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.6 4.7 v hysteresis 5.5 v < v sup < 27 v v hys 0.6 ? 1.3 v input current - 0.2 v < v in < 40 v i in -10 ? 10 a can transceiver current supply current of can module can in normal mode, bus recessive state can in normal mode, bus dominant state without bus load can in sleep state, wake-up enabled, v2 regulator off can in sleep state, wake-up disabled, v2 regulator off (25) i res i dom i can-sleep i dis ? ? ? ? 1.3 1.5 12 ? 3.0 3.5 24 1.0 ma ma a a notes 25. guaranteed by design; it is not production tested. table 5. static electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33742 electrical characteristics static electrical characteristics pins (canh and canl) bus pin common mode voltage v cm - 27 ? 40 v differential input voltage (common mode between - 3.0 v and 7.0 v) recessive state at rxd dominant state at rxd v canh - v canl ? 900 ? ? 500 ? mv differential input hysteresis (rxd) v hys 100 ? ? mv input resistance r in 5.0 ? 100 k ? differential input resistance r ind 10 ? 100 k ? canh output voltage txd dominant state txd recessive state v canh 2.75 ? ? ? 4.5 3.0 v canl output voltage txd dominant state txd recessive state v canl 0.5 2.0 ? ? 2.25 ? v differential output voltage txd dominant state txd recessive state vo h - vo l 1.5 ? ? ? 3.0 100 v mv output current capability (dominant state) canh canl i canh i canl ? 35 ? ? - 35 ? ma overtemperature shutdown t sd 160 180 ? c canl overcurrent detection (26) canl canh i canl /oc i canh /oc 60 - 200 ? ? 200 - 60 ma canh and canl input current, device supplied (can sleep mode with can wake-up enabled or disabled) v canh , v canl from 0 v to 5.0 v v canh , v canl = - 2.0 v v canh , v canl = 7.0 v i can1 ? - 60 ? 3.0 - 50 60 10 ? 75 a canh and canl input current, device unsupplied v canh , v canl = 2.5 v v canh , v canl = - 2.0 v v canh , v canl = 7.0 v i can2 ? - 60 ? 40 - 50 190 100 ? 240 a notes 26. reported in can register. for a description of the contents of the can register, refer to can register (can) on page 44 table 5. static electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 33742 electrical characteristics static electrical characteristics diagnostic information (canh and canl) canl to gnd threshold v lg ? 1.75 ? v canh to gnd threshold v hg ? 1.75 ? v canl to vsup threshold v lvb ? v sup - 2.0 ? v canh to vsup threshold v hvb ? v sup - 2.0 ? v canl to vdd threshold v l5 ? v dd - 0.43 ? v canh to vdd threshold v h5 ? v dd - 0.43 ? v rxd weak pull-down current source (27) rxd permanent dominant failure condition i rxdw ? 100 ? a pins (txd and rxd) txd input high voltage v ih 0.7 v dd ? v dd + 0.4 v txd input low voltage v il - 0.4 ? 0.3 v dd v txd high-level input current v txd = v 2 i ih -10 ? 10 a txd low-level input current v txd = 0 v i il -150 - 100 - 50 a rxd output high voltage i rxd = 250 a v oh v dd - 1.0 ? ? v rxd output low voltage i rxd = 1.0 ma v ol ? ? 0.5 v notes 27. guaranteed by design; it is not production tested. table 5. static electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 17 33742 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 6. dynamic electrical characteristics characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit digital interface timing (sclk, cs , mosi, miso) (28) spi operation frequency f req 0.25 ? 4.0 mhz sclk clock period t pclk 250 ? n/a ns sclk clock high time t wsclkh 125 ? n/a ns sclk clock low time t wsclkl 125 ? n/a ns falling edge of cs to rising edge of sclk t lead 100 ? n/a ns falling edge of sclk to rising edge of cs t lag 100 ? n/a ns mosi to falling edge of sclk t sisu 40 ? n/a ns falling edge of sclk to mosi t sih 40 ? n/a ns miso rise time (29) c l = 220 pf t rso ? 25 50 ns miso fall time (29) c l = 220 pf t fso ? 25 50 ns time from falling or rising edges of cs miso low impedance miso high impedance t soen t sodis ? ? ? ? 50 50 ns time from rising edge of sclk to miso data valid 0.2 v dd miso 0.8 v dd , c l = 200 pf t valid ? ? 50 ns state machine timing ( cs , sclk, mosi, miso, wdog , int ) delay between cs low-to-high transition (at end of spi stop command) and stop mode activation (30) t cs -stop 18 ? 34 s interrupt low-level duration stop mode t int 7.0 10 13 s internal oscillator frequency (31) f osc ? 100 ? khz watchdog period normal and standby modes period 1 period 2 period 3 period 4 t wdog 8.58 39.6 88 308 9.75 45 100 350 10.92 50.4 112 392 ms notes 28. see figure 7, spi timing diagram , page 21 . 29. not production tested. guaranteed by design. 30. not production tested. guaranteed by design. detected by v2 off. 31. f osc is indirectly measured (1.0 ms reset) and trimmed.
analog integrated circuit device data 18 freescale semiconductor 33742 electrical characteristics dynamic electrical characteristics state machine timing ( cs , sclk, mosi, miso, wdog , int ) (continued) normal request mode timeout normal request mode t nrtout 308 350 392 ms watchdog period stop mode period 1 period 2 period 3 period 4 t wd-stop 6.82 31.5 70 245 9.75 45 100 350 12.7 58.5 130 455 ms watchdog period accuracy normal and standby modes stop mode t acc -12 - 30 ? ? 12 30 % cyclic sense / fwu timing sleep and stop modes timing 1 timing 2 timing 3 timing 4 timing 5 timing 6 timing 7 timing 8 t csfwu 3.22 6.47 12.9 25.9 51.8 66.8 134 271 4.6 9.25 18.5 37 74 95.5 191 388 5.98 12 24 48.1 96.2 124 248 504 ms cyclic sense on time sleep and stop modes. t on 200 350 500 s cyclic sense / fwu timing accuracy sleep and stop modes t acc - 30 ? 30 % delay between spi command and hs turn on (32) normal or standby mode, v sup > 9.0 v t s-hson ? ? 22 s delay between spi command and hs turn off (32) normal or standby mode, v sup > 9.0 v t s-hsoff ? ? 22 s delay between spi and v2 turn on (32) standby mode t s-v2on 9.0 ? 22 s delay between spi and v2 turn off (32) normal mode t s-v2off 9.0 ? 22 s delay between normal request and normal mode after watchdog trigger command (32) normal request mode t s-nr2n 15 35 70 s notes 32. delay starts at falling edge of clock cycle #8 of the spi command and start of ?turn on? or ?turn off? of hs or v2. table 6. dynamic electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 19 33742 electrical characteristics dynamic electrical characteristics state machine timing ( cs , sclk, mosi, miso, wdog , int ) (continued) delay between spi and can normal mode (33) normal mode (34) t s-can_n ? ? 10 s delay between spi and can sleep mode (33) normal mode (34) t s-can_s ? ? 10 s delay between cs wake-up ( cs low to high) and device in normal request mode (vdd on and rst high) stop mode t w- cs 15 40 90 s delay between cs wake-up ( cs low to high) and first accepted spi command device in stop mode after wake-up t w-spi 90 ? n/a s delay between int pulse and first spi command accepted device in stop mode after wake-up t s-1stspi 20 ? n/a s delay between two spi messages addressing the same register t 2spi 25 ? ? s output pin (vdd) reset delay time measured at 50% of reset signal t d 4.0 ? 30 s i dd overcurrent to wake-up deglitcher time (34) t idd-dglt 40 55 75 s output pin ( rst ) reset duration after vdd high 33742 33742s t rst dur t rst durs 12 3.0 15 3.5 18 4.0 ms input pins (l0, l1, l2, and l3) wake-up filter time t wuf 8.0 20 38 s notes 33. delay starts at falling edge of clock cycle #8 of the spi command and start of ?turn on? or ?turn off? of hs or v2. 34. guaranteed by design; it is not production tested. table 6. dynamic electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 20 freescale semiconductor 33742 electrical characteristics dynamic electrical characteristics can module ? signal edge rise and fall times (canh, canl) dominant state timeout t dout 200 360 520 s propagation loop delay txd to rxd (recessive to dominant) (35) slew rate 3 slew rate 2 slew rate 1 slew rate 0 t lrd 60 70 80 110 100 110 130 200 210 225 255 310 ns propagation delay txd to can (recessive to dominant) (36) slew rate 3 slew rate 2 slew rate 1 slew rate 0 t trd 20 25 35 50 65 80 100 160 110 150 200 300 ns propagation delay can to rxd (recessive to dominant) (37) t rrd 10 50 140 ns propagation loop delay txd to rxd (dominant to recessive) (35) slew rate 3 slew rate 2 slew rate 1 slew rate 0 t ldr 100 120 140 250 150 165 200 340 200 220 250 410 ns propagation delay txd to can (dominant to recessive) (36) slew rate 3 slew rate 2 slew rate 1 slew rate 0 t tdr 60 65 75 200 125 150 180 310 150 190 250 460 ns propagation delay can to rxd (dominant to recessive) (37) t rdr 20 30 60 ns non-differential slew rate (canl or canh) slew rate 3 slew rate 2 slew rate 1 slew rate 0 t sl3 t sl2 t sl1 t sl0 4.0 3.0 2.0 1.0 19 13.5 8.0 5.0 40 20 15 10 v/ s bus communication rate t bus 60k ? 1.0m bps ???? 35. see figure 8 , page 21 . 36. see figure 9 , page 21 . 37. see figure 10 , page 21 . table 6. dynamic electrical characteristics (continued) characteristics noted under conditions 4.75 v v2 5.25 v, 5.5 v v sup 18 v, and -40 c t a 125 c. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 21 33742 electrical characteristics timing diagrams timing diagrams figure 7. spi timing diagram figure 8. propagation loop delay txd to rxd figure 9. propagation delay txd to can figure 10. propagation delay can to rxd di 0 do 0 undefined don?t care di 8 don?t care t lead t sisu t wsclkh do 8 cs sclk mosi miso note incoming data at mosi pin is sampled by the 33742 at sclk falling edge. outgoing data at miso pin is set by the 33742 at sclk rising edge (after t valid delay time). t sih t wsclkl t lag t valid t soen t sodis t pclk txd 0.8 v t lrd 0.8 v rxd t ldr 2.0 v 2.0 v txd 0.8 v t trd 0.9 v v diff 2.0 v 0.5 v t tdr v diff = v canh - v canl v diff 0.9 v t rrd 2.0 v t rdr 0.8 v rxd 0.5 v
analog integrated circuit device data 22 freescale semiconductor 33742 functional description introduction functional description introduction the 33742 and the 33742s are system basis chips (sbcs) dedicated to automotive applications. their functions include the following: ? one fully protected 5.0 v voltage regulator with 200 ma total output current capability available at the vdd pin. ? vdd regulator undervol tage reset function, programmable window or time-out software watchdog function. ? internal driver (v2) for an external series pass transistor to implement a second 5.0 v voltage regulator. ? two running modes: normal and standby modes set by the system microcontroller. ? sleep and stop modes low power operating modes to reduce an application?s cu rrent consumption while providing a wake-up capability from the can interface, l3 : l0 wake-up inputs, or from a timer wake-up. ? programmable wake-up input and cyclic sense wake- ups. ? can high-speed physical bus interface with txd and rxd fault diagnostic capability and enhanced protection features. ? an spi interface for use in communicating with a mcu and interrupt outputs to report sbc status, perform diagnostics, and report wake-up events. functional pin description receive and transmit data (rxd and txd) the rxd and txd pins (receive data and transmit data pins, respectively) are connected to a microcontroller?s can protocol handler. txd is an input and controls the canh and canl line state (dominant when txd is low, recessive when txd is high). rxd is an output and reports the bus state (rxd low when can bus is dominant, high when can bus is recessive). voltage digital drain (vdd) the vdd pin is the output pin of the 5.0 v internal regulator. it can deliver up to 200 ma. this output is protected against overcurrent and overtemperature. it includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130c typical. when the temperature exceeds th e overtemperature shutdown (170c typical), the regulator is turned off. vdd includes an undervoltage reset circuitry, which sets the rst pin low when vdd is below the undervoltage reset threshold. reset output ( rst) the reset pin rst is an output that is set low when the device is in reset mode. the rst pin is set high when the device is not in reset mode. rst includes an internal pullup current source. when rst is low, the sink current capability is limited, allowing rst to be shorted to 5.0 v for software debug or software download purposes. interrupt output ( int ) the interrupt pin int is an output that is set low when an interrupt occurs. int is enabled using the interrupt register (intr). when an interrupt occurs, int stays low until the interrupt source is cleared. int output also reports a wake-up event by a 10 s typical pulse when the device is in stop mode. voltage source 2 (v2) the v2 pin is the input sense for the v2 regulator. it is connected to the external series pass transistor. v2 is also the 5.0 v supply of the internal can in terface. it is possible to connect v2 to an external 5.0 v regulator or to the vdd output when no external series pass transistor is used. in this case, the v2ctrl pin must be left open. refer to figure 31, sbc typical application schematic , page 52 . voltage source 2 control (v2ctrl) the v2ctrl pin is the output drive pin for the v2 regulator connected to the external series pass transistor. voltage supply (vsup) the vsup pin is the battery supply input of the device. high-side output (hs) the hs pin is the internal high-side driver output. it is internally protected against overcurrent and overtemperature. level 0-3 inputs (l0: l3) the l0 : l3 pins can be connected to contact switches or the output of other ics for external inputs. the input states can be read by spi. these inputs can be used as wake-up events for the sbc when operating in the sleep or stop mode. can high and can low outputs (canh and canl) the can high and can low pins are the interfaces to the can bus lines. they are contro lled by txd input level, and the state of canh and canl is reported through rxd output. a 60 ? termination resistor is connected between canh and canl pins.
analog integrated circuit device data freescale semiconductor 23 33742 functional description functional pin description serial data clock (sclk) sclk is the serial data clock input pin of the serial peripheral interface. master in slave out (miso) miso is the master in slave out pin of the serial peripheral interface. data is sent from the sbc to the microcontroller through the miso pin. master out slave in (mosi) mosi is the master out slave in pin of the serial peripheral interface. control data from a microcontroller is received through this pin. chip select ( cs ) cs is the chip select pin of the serial peripheral interface. when this pin is low, the spi port of the device is selected. watchdog output ( wdog ) the watchdog output pin is asse rted low to flag that the software watchdog has not been properly triggered.
analog integrated circuit device data 24 freescale semiconductor 33742 functional device operation operational modes functional device operation supply voltage at vsup the 33742 receives its oper ating voltage via the vsup pin. an external diode is needed in series with the vsup pin and the supply voltage to protect the sbc against negative transients or from a reverse batte ry situation that can occur in a vehicle application. the 33742 will operate from a supply voltage input as low as 4.5 vdc to as high as 27 vdc. the later voltage is often encounter ed during a vehicle jump-start. the vsup pin can tolerate automotive transient conditions such as load dump to 40 v. the sbc is able to detect when v sup falls below 3.0 v typical. this undervoltage state is detected and retained in the parts mode control register (mcr) as the batfail bit. this detection capability is available across all operating modes. note for a detailed description of all the registers mentioned in this section, refer to the section titled spi interface and register description beginning on page 42 . the sbc incorporates a v sup level early warning function, which provides a maskable interr upt if the vsup voltage level falls below 6.0 v typical. hysteresis is used to reduce false detections. the early warning function works only in normal and standby operation modes. an undervoltage at the vsup pin is reported in the input / output register (ior). vdd regulator the vdd regulator provides a 5.0 v low dropout voltage capable of supplying up to 200 ma with monitoring circuitry for undervoltage detection and a reset function. the vdd regulator is protected against overcurrent and short circuit conditions. it has overtemper ature detection and will set warning flags (bit vddtemp in the mcr and intr registers) and has overtemperature s hutdown with hysteresis. v2 regulator the v2 regulator feature provides for a second 5.0 vdc voltage source the internal v2 circuitry will drive an external series pass transistor, substantially increasing the available supply current. two pins, the v2 and the v2ctrl, are used to sense and drive the series pass transistor. the output voltage is 5.0 v and tracks the vdd regulator. the mjd32c transistor is recommended for use as the external pass device. other pnp transistors can be used but depending on the device?s gain, an external resistor-capacitor network might be needed. v2 is also the supply voltage for the on- board can module. an undervoltage condition for the v2 voltage is reported in the ior register (bit v2low set to logic [1] if v2 falls below 4.0 v typical). hs vsup switch output the hs output is a 2.0 ? typical switch tied to the vsup pin. it can power or bias external switches and their associated pullup or put-downs or other circuitry. an example is biasing a set of switches connected to the l0 : l3 wake-up input pins. the hs vsup out put current is limited to 200 ma and is protected against short circuits conditions and will report an overtemperature shutdown condition (bit hsot in the ior register and bit hsot - v2low in the intr register). the hs output ?on? state is se t by the hson bit in the ior register. a cyclic mode of operation can be implemented using an internal timer in the sleep and stop operating modes. it can also be turned on in normal or standby modes to drive loads or supply peripheral components. no internal protection circuitry is provid ed, however. dedicated chip protection circuitry is required for inductive load applications. the hs output pin should not go below - 0.3 v. battery fail early warning refer to the discussion under the heading, supply voltage at vsup above. internal clock the 33742 has an internal clock used to generate all timings (reset, watchdog, cyclic wa ke-up, filtering time, etc.). there are two on-board oscillators;: a higher accuracy (12 percent) oscillator used in normal request, normal, and standby modes,; and a lower accuracy (30 percent) oscillator used during sleep and stop modes. operational modes introduction the 33742 has four modes of op eration, all controllable via the spi. the modes are standby, normal, stop, and sleep. an additional temporary mode called normal request mode is automatically accessed by the device after reset or wake- up from stop mode. a reset mode is also implemented. special modes and configurations are possible for debug and program microcontroller flash memory. table 7 , page 25 , offers a summary of the functional modes. standby mode in standby mode only the vdd regulator is on. the v2 regulator is turned off by disabling the v2ctrl pin. other functions available are the l0 : l3 inputs read through via the spi and hs output activation. the can interface is not able to send messages. if a can message is received, the canwu bit is set. the watchdog timer is running.
analog integrated circuit device data freescale semiconductor 25 33742 functional device operation operational modes normal mode in normal mode, both the vdd and v2 regulators are in the on state. all functions are ava ilable in this operating mode (watchdog, wake-up input reading through spi, hs activation, and can communication). the watchdog timer is running and must be periodically cleared through spi. stop mode the v2 regulator is turned off by disabling the v2ctrl pin. the vdd regulator is activated in a special low power mode supplying only a few ma of current. this maintains ?keep alive? power for the application?s mcu while the mcu is in a power-saving state (i.e ., a mcu?s version of stop or wait). in the stop mode, the supply current available from vsup pin is very low. both parts (the sbc or the mcu) can be awakened from either the 33742 side (for ex ample, cyclic sense, forced wake-up, can message, wake-up inputs, and overcurrent on vdd) or from the mcu side (key wake-up, etc.). stop mode is always selected via spi. in stop mode, the watchdog software may be either running or not running depending upon selection by spi (reset control register [rcr], bit wdstop). to clear a running watchdog timer, the sbc must be awakened using the cs pin (spi wake-up). in stop mode, wake-up is identical to that in sleep mode, with the addition of cs and vdd overcurrent wake-up. refer to table 7 , page 25 . sleep mode in sleep mode, the vdd and v2 regulators are off. current consumption from the vsup pin is cut. in sleep mode, the sbc can be awakened by sensing individual level individual level changes in the l0 : l3 inputs, by cyclic checking of the l0 : l3 inputs, by the forced wake-up timer, or from the can physical interface upon receiving a can message. when a wake-up occurs, the sbc goes first into the reset mode before entering normal request mode. reset mode in the reset mode, the rst pin is low and a timer runs for t rst dur time. after t rst dur has elapsed, the 33742 enters the normal request operating mode. the reset mode is entered if a reset condition occurs (vdd low, watchdog time-out, or watchdog trigger in a closed window). normal request mode the normal request mode is a temporary operating mode automatically entered by the sbc after the reset mode or after the 33742 wakes up from the stop mode. after a wake-up from the sleep mode or after a device power-up, the sbc enters the reset mode prior to entering the normal request mode. after a wake-up from the stop mode, the 33742 enters the normal request mode directly. in normal request mode, the vdd regulator is on, the v2 regulator is off, and the rst pin is high. as soon as the sbc enters the normal request mode, an internal 350 ms timer is started (parameter t nrtout ). during this time, the application?s mcu must address the 33742 via spi and configure the tim1 sub regist er to select the watchdog period. this is required of the sbc to stop the 350 ms watchdog timer and enter the normal or standby mode and to set the watchdog timer configuration. normal request entered and no watchdog configuration occurs if the normal request mode is entered after the sbc powers up or after a wake-up from stop mode and no watchdog configuration occurs before the 350 ms time period has expired, the device en ters the reset mode. if no watchdog configuration is performed, the 33742 will cycle from the normal request mode to reset mode to normal request mode. if the normal request mode is entered after a wake-up from sleep mode, and no watchdog configuration occurs while the 33742s is in normal request mode, the sbc returns to the sleep mode. table 7. table of operations mode voltage regulator hs switch wake-up capabilities (if enabled) rst pin int pin watchdog software can cell normal request vdd: on, v2: off, hs: off ? low for t rst dur time, then high ? ? ? normal vdd: on, v2: on, hs: controllable ? normally high. active low if wdog or v dd undervoltage occurs if enabled, signal failure (vdd pre-warning temp, can, hs) running txd / rxd standby vdd: on, v2: off, hs: controllable ? same as normal mode same as normal mode running low power
analog integrated circuit device data 26 freescale semiconductor 33742 functional device operation operational modes application wake-up from the 33742 when the application is in st op mode, it can be awakened from the sbc side. when a wake -up condition is detected by the sbc (for example, can, wake-up input), the 33742 enters the normal request mode and generates an interrupt pulse at the int pin. application wake-up from the mcu when the device is in the stop mode, a wake-up event may come from the system mcu. in this case the mcu selects the device the using a low-to-high transition on the 33742 cs pin. then the 33742s goes into normal request mode and generates an interrupt pulse at the int pin. stop mode current monitor if the vdd output current exceeds an internal set threshold (i dds-wu ), the sbc automatically enters the normal request mode and generates an interrupt at the int pin. the interrupt is a non-maskable and the intr register will have no flag set. interrupt generation when wake-up from stop mode when the sbc wakes from stop mode, it first enters the normal request mode before generating a 10 s typical pulse on the int pin. these are non-maskable interrupts with the wake-up event read through the spi registers, the canwu bit in the can register (canr), or the lctrx bit in the wake-up register (wur). in case of wake-up from stop mode overcurrent situation or from forced wake-up, no bits are set. after the int pulse, the 33742 accepts spi command after a time delay (t s-1stspi ). watchdog software in stop mode if the sbc watchdog is enabled, the application must provide a ?system ok? response before the end of the 33742 watchdog time. typically an mcu initiates the wake-up of the 33742 through the spi wake-up ( cs activation). the sbc will awaken and jump into the normal request mode. the mcu has to configure the 33742 to go to either normal or standby mode. the mcu can then decide to return to the stop mode. if no mcu wake-up occurs within the watchdog time period, the sbc activates the rst pin and jumps into the normal request mode. the mcu can then be re-initialized. stop mode enter command stop mode is entered at the end of the spi message at the rising edge of the cs . (refer to the t cs -stop data in the dynamic electrical characteristics table on page 17 .) once stop mode is entered, the sbc can wake up from a vdd regulator overcurrent detection st ate. in order to allow time for the mcu to complete the last cpu instruction and enter its low power mode, a deglitcher time of 40 s typical is implemented. figure 11 , page 27 , depicts the operation of entering the stop mode. stop vdd: on (limited current capability), v2: off, hs:off or cyclic sense can, spi, l0 : l3, cyclic sense, forced wake-up, i dd overcurrent (39) normally high. active low if wdog (40) or vdd undervoltage occurs signal 33742s wake-up and i dd > i dds-wu (not maskable) running if enabled. not running if disabled low power. wake-up capability if enabled sleep vdd: off, v2: off, hs: off or cyclic can, spi, l0 : l3, cyclic sense forced wake-up low not active not running low power. wake-up capability if enabled normal debug (38) same as normal ? normally high. active low if vdd undervoltage occurs same as normal not running same as normal standby debug (38) same as standby ? normally high. active low if vdd undervoltage occurs same as standby not running same as standby stop debug (38) same as stop same as stop normally high. active low if vdd undervoltage occurs same as stop not running same as stop flash programming forced externally ? not operating not operating not operating not operating notes 38. mode entered via special sequence described under the heading debug mode: hardware and software debug with the 33742 beginning on page 30 . 39. i dd overcurrent always enabled. 40. wdog if enabled.
analog integrated circuit device data freescale semiconductor 27 33742 functional device operation operational modes figure 11. enteri ng the stop mode watchdog software ( rst and wdog ) (selectable watc hdog window or watchdog time-out) a watchdog is used in the sbc normal and standby modes for monitoring the mcu operation. the watchdog timer may be implemented as either a watchdog window or watchdog time-out, selectable by spi (tim1 sub register, bit wdw). default operation is a watchdog window. the watchdog period can be set from 10 ms to 350 ms (tim1 sub register, bits wdt0 and wdt1). when a watchdog window is selected, the closed window is the first part of the selected period, and the open window is the second part of the period. (refer to timing register (tim1 / 2) beginning on page 47 .) the watchdog can only be cleared within the open window time period. any attempt to clear watchdog in the closed window will generate a reset. the watchdog is cleared addressing the tim1 sub register using the spi rst pin description a 33742 output is available to perform a reset of the mcu. reset can happen from: ? vdd falling out of range ? if vdd falls below the reset threshold (v rst th ), the rst pin is pulled low until vdd returns to the normal voltage. ? power-on reset ? at 33742 power-on or wake-up from sleep mode, the rst pin is maintained low until vdd is within its operation range. ? watchdog time-out ? if watchdog is not cleared, the 33742 will pull the rst pin low for the duration of the reset time (t rst dur ). rst and wdog operation table 8 describes watchdog and reset output modes of operation. rst is activated in the event vdd fall or watchdog is not triggered. wdog output is active low as soon as rst goes low and stays low as long as the watchdog is not properly reset via spi. the wdog output pin is designed as a push-pull structure that can drive off chip components signaling, for instance, errant mcu operation. figure 12 illustrates the device behavior in the event the tim1 register in not properly accessed. in this case a software reset occurs, and the wdog pin is set low until the tim1 register is properly accessed. spi cs spi stop/sleep command 33742 in normal or stand-by mode 33742 in stop mode. no i dd over i dd-dglt 33742 in stop mode. i dd over i dd-dglt t cs -stop tidd-dglt table 8. watchdog and reset output operation events wdog output rst output device power-up low to high low to high vdd normal, wdog properly triggered high high vdd < v rst th high low wdog time-out reached low (41) low notes 41. wdog stays low until the tim1 register is properly addressed through spi.
analog integrated circuit device data 28 freescale semiconductor 33742 functional device operation operational modes figure 12. rst and wdog output operation wake-up capabilities several wake-up capabilities are available to the sbc when it is in sleep or stop mode. when a wake-up has occurred, the wake-up event is stored in the wake-up register (wur) or the can regi ster and read by the mcu to determine the wake-up source. the wake-up options are selectable through spi while the 33742 is in normal or standby mode and prior to entering low power modes (sleep or stop mode). when a wake-up occurs in sleep mode, the sbc reactivates vdd supply. it generates an interrupt if wake-up occurs from stop mode. wake-up from wake-up inputs (l0 : l3) without cyclic sense the wake-up lines are used to determine the state of external switches and if changes occurred to wake up the mcu (in sleep or stop modes). wake-up pins l0 : l3 are able to handle up to 40 vdc. the internalize? threshold is 3.0 v typical and these inputs can be used as an input port expander. the wake-up input st ates are read through spi (wur register). in order to select and activate direct wake-up from the l0 : l3 inputs, the wur register must be configured with the appropriate level sensitivity. additionally, the low power control (lpc) register must be configured with 0xx0 data (bits lx2hs and hsauto are set to 0). the sensitivity of the l0 : l3 inputs is selected by the wur register. level sensitivity is configured by l0 : l3 input pairs: l0 and l1 level sensitivity are configured together, while l2 and l3 are configured together. cyclic sense wake-up (cyclic sense timer and wake-up inputs l0 : l3) the 33742 can wake up upon state change of one of the four wake-up input lines (l0 : l3). the external pullup or pull- down resistor of the switches associated with the wake-up input lines can be biased from the hs vsup switch. the hs switch is activated in sleep or stop modes from an internal timer. cyclic sense and forced wake-up are exclusive states. if cyclic sense is enabled, forced wake-up cannot be enabled. in order to select and activate the cyclic sense wake-up from the l0 : l3 inputs, the wur register must be configured with the appropriate level sens itivity and the lpc register must be configured with 1xx1 dat a (bit lx2hs set at 1 and bit hsauto set at 1). the wake-up mode selection (direct or cyclic sense) is valid for all four wake-up inputs. forced wake-up the sbc can wake up automatically after a predetermined time spent in sleep or stop mode. cyclic sense and forced wake-up are exclusive. if forced wake-up is enabled (fwu bit set to 1 in the lpc regist er), cyclic sense cannot be enabled. can interface wake-up the sbc incorporates a high-speed 1.0 mbps can physical interface. it is compatible with iso 11898-2 standard. the operation of the can physical interface is controlled through the spi. the can operating modes are independent of the 33742 operational modes. the sbc can wake up from a can message if the can wake-up feature is enabled. refer to the section titled logic commands and registers beginning on page 42 for details of the wake-up detection. spi wake-up the 33742 can be awakened by changes on the cs pin in sleep or stop modes. wake- up is detected as a low-to- high level transition on the cs pin. in the stop mode, this corresponds to a condition where an mcu and the sbc are both in the stop mode and when the application wake-up event comes through the mcu. 33742 power-up and wake-up from sleep mode after device or system po wer-up, or after the sbc awakens from sleep mode, the 33742s enters into the reset mode prior to moving in to normal request mode. figure 13 , shows the device state diagram. figure 14 , shows device operation after power-up. rst wdog vdd spi spi cs watchdog time-out tim1 register addressed. watchdog period wdog clear
analog integrated circuit device data freescale semiconductor 29 33742 functional device operation operational modes figure 13. sbc state diagram (not valid in debug modes) figure 14. operation after sbc power-up notes 42. these two spi commands must be s ent consecutively in this sequence. 43. if watchdog activated. w at c h do g: trigger (v dd high temperature or [v dd low > 100 ms & v sup > bfew]) & nostop &!batfail watchdog: time-out & nostop &!batfail power down reset normal request stop sleep reset counter (3.4 ms) expired 33742s power- v dd low or watchdog: timeout 350 ms & nostop 1 wake-up spi: stand-by and watchdog trigger 3 spi: standby spi: normal spi: stop & cs low to high transition spi: stop & cs low to h igh tra n s i tion 4 2 watchdog: timeout or v dd low nostop and spi: sleep & cs low to high nostop and spi: sleep & cs low to high transition 1 watchdog: timeout or v dd low 1 2 w a t c h d o g : t i m e - o u t o r v d d l o w ( 4 3 ) 1 wake-up 1 2 3 4 denotes priority state machine description nostop = nostop bit = 1 ! nostop = nostop bit = 0 batfail = batfail bit = 1 ! batfail = batfail bit = 0 v dd overtemperature = v dd thermal shutdown occurs v dd low = v dd below reset threshold v dd low > 100 ms = v dd below reset threshold for more than 100 ms watchdog: trigger = tim1 subregister write operation v sup > bfew = v sup > battery fail early warning (6.1 v typical) watchdog: timeout = tim1 register not written before watchdog timeout period expired, or watchdog written in incorrect time window if watchdog window selected (except stop mode). in normal request mode, timeout is 355 ms p2.2 (350 ms p3) ms. spi: sleep = spi write command to mcr register, data sleep spi: stop = spi write command to mcr register, data stop spi: normal = spi write command to mcr register, data normal spi: standby = spi write command to mcr register, data standby normal standby power-up reset normal request normal trigger batfail no stop sleep no no yes no yes yes operation after power-up if no trigger appears operation after reset of batfail if no trigger appears
analog integrated circuit device data 30 freescale semiconductor 33742 functional device operation operational modes debug mode: hardware and software debug with the 33742 when a sbc, and the mcu it serves, is used on the same printed circuit board, both the mcu software and the 33742 operation must be debugged concurrently. the following features permit system debugging by allowing the disabling of the sbc internal so ftware watchdog timer. device power-up, reset pin connected to vdd the vdd voltage is available when the 33742 power-up but the 33742 will not have received any spi communication to configure itself. until set up by the system mcu, the 33742 will generate a reset every 350 ms until the part is configured. to avoid continuous mcu hardware resets, the 33742?s rst pin can be connected directly to vdd pin by a hardware jumper. debug modes with software watchdog disabled though spi (normal debug, standby debug, and stop debug) the software configurable watchdog can be disabled through spi. to set the watchdog disable while limiting the risk of inadvertently disabling the watchdog timer during normal 33742 operation, it is recommended that the disable be done using the following sequence: ? step 1? power down the sbc. ? step 2 ? power up the sbc. this sets the batfail bit, allowing the 33742 to enter normal request mode. ? step 3 ? write to the tim1 sub register to allow the sbc to enter normal mode. ? step 4 ? write to the mcr register with data 0000. this enables the debug mode. complete spi byte is 0001 0000. ? step 5 ? write to the mcr register normal debug. spi byte is 0001 x101. important while in debug mode, the sbc can be used without having to clear the watchdog on a regular basis to facilitate software and hardware debug. ? step 6 ? to leave the debug mode, write 0000 to the mcr register. at step 2, the sbc is in no rmal request. steps 3, 4, and 5 should be completed consecutively and within the 350 ms time period of the normal re quest mode. if not, the 33742 will go into reset mode and enter normal request again. figure 15 , page 30 , illustrates debug mode selection. figure 15. entering debug mode when the sbc is operating in the debug mode and has been set into stop debug or sleep mode, a wake-up causes the 33742 to enter the normal request mode for 350 ms. to avoid having the sbc generate an unwanted reset (enter reset mode), the next debug mode (normal debug or standby debug) should be configured within the 350 ms time window of the normal request mode. to avoid entering debug mode after a power-up, first read the batfail bit (mcr read) and write 0000 into the mcr register. figures 16 and 17 , page 31 , show the detailed operation of the sbc once the debug mode has been selected. v sup spi mcr (step 4) batfail vdd debug mode mcr (step 5) spi: read batfail mcr (step 6) 33742 in debug mode. 33742 not in debug mode. tim1(step 3) no watchdog watchdog on
analog integrated circuit device data freescale semiconductor 31 33742 functional device operation operational modes figure 16. transitions to enter debug modes figure 17. simplified 33742s state diagram in debug modes normal request standby debug spi: mcr (0000) and normal debug normal w a t c h d o g : t r i g g e r reset reset counter (3.4 ms) expired watchdog: timeout 350 ms normal debug spi: mcr (0000) and standby debug power down wake-up spi: standby & watchdog: trigger wake-up normal request standby debug spi: normal debug normal w a t c h d o g : t r i g g e r standby spi: standby debug spi: standby debug s p i : n o r m a l d e b u g reset reset counter (3.4 ms) expired watchdog: time-out 350 ms &!batfail & nostop & spi: sleep spi: normal debug normal debug sp i: st a ndb y d eb ug stop debug spi: stop wake-u p e e spi: stop debug & cs low to high transition r r r r r r r r (1) if stop mode is entered, it is entered without watchdog, no matter the wdstop bit. (e) debug mode entry point (step 5 of the debug mode entering sequence). (r) represents transitions to reset mode due to v1 low. sleep stop (1)
analog integrated circuit device data 32 freescale semiconductor 33742 functional device operation operational modes mcu flash programmi ng configuration to allow for new software to be loaded into a sbc?s mcu nvm or to standalone eeprom or flash, the 33742 is capable of having (1) vsup applied to it to from an external power 5.0 v supply and (2) having the rst and the wdog outputs pins eternally forced to 0.0 v or 5.0 v without damaging the device. this allows the sbc to be externally powered and off- board signals to be applied to the reset pins. no functions of the 33742 are operating. figure 18 illustrates a typical configuration for the connection of programming and debugging tools. the vsup should be left open or forced to a value equal to or above v. the vdd regulator uses an internal pass transistor between vsup and the vdd output pin. biasing the vdd output pin with a voltage greater than vdd potential will force current through the body diode of the internal pass transistor to the vsup pin. the rst pin is periodically pulled low for the t rst dur time (device in reset mode), before being pulled to vdd for 350 ms typical (device in normal request mode). during the time reset is low, the rst pin sinks 5.0 ma maximum (i pdw ). figure 18. simplified schematic for microcontroller flash programming 33742 mcu with vdd rst wdog vsup (open or > 5.0 v programming bus note external supply and sources applied to vdd, rst , and wdog test points on application circuit board. 5.0 v programming tool flash memory
analog integrated circuit device data freescale semiconductor 33 33742 functional device operation operational modes can physical interface the sbc features a high-speed can physica l interface for bus communication from 60 kbps up to 1.0 mbps. figure 19 is a simplified block diagram of the can interface of the 33742. figure 19. simplified bl ock diagram of can interface can interface supply the supply voltage for the can transceiver is the v2 pin. the can interface also has a supply path from the external supply line through the vsup pi n. this path is used in can sleep mode to allow wake-up detection. during can communication (transmission and reception), the can interface current is sourced from the v2 pin. during can low power mode, the current is sourced from the vsup pin. main operation modes description the can interface of the sbc has two main operating modes: txrx and sleep mode. the modes are controlled by the can spi register. in the txrx mode, which is used for communication, four different slew rates are available for the user. in the sleep mode, the user has the option of enabling or disabling the remote can wake-up capability. can driver operation in txrx mode when the can interface is in txrx mode, the driver has two states: recessive or dominant. the driver state is controlled by the txd pin. the bus state is reported through the rxd pin. when txd is high, the driver is set in recessive state, and canh and canl lines are biased to the voltage set at v2 divided by 2, or approximately 2.5 v. when txd is low, the bus is set into dominant state: canl and canh drivers are active. canl is pulled to ground, and canh is pulled high toward 5.0 v (voltage at v2). the rxd pin reports the bus state: canh minus canl voltage is compared versus an internal threshold (a few hundred millivolts). if canh minus canl is below the threshold, the bus is recessive and rxd is set high. if canh minus canl is above the threshold, the bus is dominant and rxd is set low. this is illustrated in figure 19 . v2 bus termination (60 ? ) canh line canl line txd rxd differential receiver driver driver 2.5 v wake-up wake-up receiver pattern recognition internal vsup wake-up signal canh canl spi control spi control spi control v2 v2 v2 v2 qh ql 33742
analog integrated circuit device data 34 freescale semiconductor 33742 functional device operation operational modes figure 20. can interface levels txd and rxd pins the txd pin has an internal pullup to v2. the state of txd depends on the v2 status. rx d is a push-pull structure, supplied by v2. when v2 is set at 5.0 v and can is txrx mode, rxd reports bus stat us. for details, refer to table 7 , page 25 , table 9 , below, and table 10 , page 35 . can txrx mode and slew rate selection the slew rate selection is done via can register (refer to tables 21 through 23 on page 45 ). four slew rates are available and control the recessive-to-dominant and dominant-to-recessive transitions. the delay time from txd pin to can bus, from can bus to rxd, and from the txd to rxd loop time is affected by the slew rate selection. canh txd rxd typ 2.5 v canl can recessive state can dominant state can recessive state typ 2.5 v v canh -v canl > 900 mv v canh -v canl < 500 mv table 9. can interface / 33742s modes and pin status?ope ration with ballast on v2 (44) mode can mode (controlled by spi) v2 voltage txd pin rxd pin canh/canl (disconnected from other node) can communication unpowered ? 0.0 v low low floating to gnd no reset (with ballast) ? 0.0 v low low floating to gnd no normal request (with ballast) ? 0.0 v low low floating to gnd no normal sleep 5.0 v 0.0 v 5.0 v floating to gnd no normal normal slew rate 0, 1, 2, 3 5.0 v internal pullup to v2 report bus state high if bus recessive, low if dominant bus recessive canh = canl = 2.5 v yes standby with external ballast normal or sleep 0.0 v low low floating to gnd no sleep sleep 0.0 v low low floating to gnd no. wake-up if enabled stop sleep 0.0 v low low floating to gnd no. wake-up if enabled notes 44. see also figure 31 , page 52 .
analog integrated circuit device data freescale semiconductor 35 33742 functional device operation operational modes can sleep mode the 33742 offers two can sleep modes: ? sleep mode with can wake-up enable: detection of incoming can message and sbc wake-up. ? sleep mode with can wake-up disable: no detection of incoming can message. the can sleep modes are set via the can spi register. in can sleep mode (with wake-up enable or disable), the can interface is internally su pplied from the vsup pin. the voltage at v2 pin can be either 5.0 v or turned off. when the can is in sleep mode, the current sourced from v2 is extremely low. in most cases t he v2 voltage is off; however, the can can be placed into sleep mode even with 5.0 v applied on v2. in can sleep mode, the canh and canl drivers are disabled, and the receiver is also disabled. canh and canl are high-impedance mode to ground. can signals in txrx and sleep modes when the can interface is set back into txrx mode by an spi command, can h and canl are set in recessive level. this is illustrated in figure 21 . table 10. can interface / 33742 modes and pin status ? operation without ballast on v2 (45) mode can mode (controlled by spi) v2 voltage txd pin rxd pin canh/canl (disconnected from other node) can communication unpowered ? 0.0 v low low floating to gnd no reset (with ballast) ? 0.0 v low low floating to gnd no normal request without ballast. v2 connected to vdd ? 5.0 v low 5.0 v floating to gnd no standby without external ballast,. v2 connected to vdd normal or sleep 5.0 v 0.0 v 5.0 v floating to gnd no normal without external ballast. v2 connected to vdd normal slew rate 0, 1, 2,3 5.0 v 5.0 v 5.0 v bus recessive canh = canl = 2.5 v yes normal without external ballast,. v2 connected to vdd sleep 5.0 v 0.0 v 5.0 v floating to gnd no sleep sleep 0.0 v low low floating to gnd no. wake-up if enabled stop sleep 0.0 v low low floating to gnd no. wake-up if enabled notes 45. see also figure 36 , page 55 .
analog integrated circuit device data 36 freescale semiconductor 33742 functional device operation operational modes figure 21. can signals in txrx and sleep modes can in sleep mode with wake-up enable when the can interface is in sleep mode with wake-up enable, the can bus traffic is detected. the can bus wake- up is a pattern wake-up. pattern wake-up in order to wake up the can interface, the following criteria must be fulfilled: ? the can interface wake-up rece iver must receive a series of three consecutive valid dominant pulses, each of which must be longer than 500 ns and shorter than 500 s. ? the distance between 2 pulses must be lower than 500 s. ? the three pulses must occur within a time frame of 1.0 ms. the pattern wake-up of the 33742 can interface allow wake-up by any can message content. figure 22 below illustrates the can signals during a can bus sleep state and wake-up sequence. figure 22. can bus signal during can sleep state and wake-up sequence canl canh txd rxd ground 2.5 v canl dominant canh dominant canl/canh recessive can in txrx mode can in sleep mode (wake-up enable or disable) can in txrx mode (controlled by spi command) canl canh txd rxd ground 2.5 v canl dominant canh dominant canl/canh recessive can in txrx mode can in sleep mode (wake-up enable) incoming can message canl dominant canh dominant canl dominant canh dominant canl dominant canh dominant wu receiver internal wake-up signal min 500 ns max 500 s can bus sleep state pulse # 1 pulse # 2 pulse # 3
analog integrated circuit device data freescale semiconductor 37 33742 functional device operation operational modes figure 23 illustrates how the wake-up signal is generated. first the can signal is detected by a low consumption receiver (wu receiver). then the signal passes through a pulse width filter, which discards the undesired pulses. the pulse must have a width bigger than 0.5 s and smaller than 500 s to be accepted. when a pulse is discarded, the pulse counter is reset and no wake-up signal is generated. when a pulse is accepted, the pulse co unter is incremented and, after three pulses, the internal wake-up signal is asserted. each one of the pulses must be spaced by no more than 500 s. if not, the counter will be reset and no wake-up signal will be generated. this is accomplished by the wake-up timeout generator. the wake-up cycle is completed (and the wake-up flag reset) when the ca n interface is brought to can normal mode. figure 23. wake-up functional block diagram can wake-up report the can wake-up reporting depend upon the low power mode the sbc is in. if the sbc is placed into slee p mode (vdd and v2 off), the can wake-up or any wake-up results in the vdd regulator turning on, leading to turning on the mcu supply and releasing reset. if the 33742 is in stop mode (v2 off and vdd active), the can wake-up or any wake-up is signalled by a pulse on the int output. in addition the canwu bit is set in the can register. if the sbc is in normal or standby mode and the can interface is in sleep mode with wake-up enabled, the can wake-up is reported by the canwu bit in the can register. in the event the sbc is in normal mode and can sleep mode with wake-up enabled, it is recommended that the user check for the canwu bit prior to placing the 33742 in sleep or stop mode in case bus traffic has occurred while the can interface was in sleep mode. after a can wake-up, a flag is set in the can register. bit canwu reports the can wake-up event while the 33742 was in sleep or stop mode. this bit is set until the can is in placed by spi command into txrx mode and the can register can be read. can bus diagnostic the sbc can diagnose canh or canl lines short to gnd, shorts to vsup or vdd. as illustrated in figure 24 , several single-ended comparators are implemented on the canh and canl bus lines. these comparators monitor the bus voltage level in the recessive and dominant states. this information is then managed by a logic circuit to determine if a failure has occurred and to report it. table 11 indicates the state of the comparators in the event of bus failure and the state of the drivers; that is, whether t hey are recessive or dominant. + internal wake-up latch rst time-out rst counter pulse ok narrow pulse pulse width filter time-out generator standby wu receiver canh canl signal
analog integrated circuit device data 38 freescale semiconductor 33742 functional device operation operational modes figure 24. can bus simplified structure table 11. short to gnd, short to vsup , and short to 5.0 v (vdd) detection truth table failure description driver recessive state driver dominant state lg (threshold 1.75 v) hg (threshold 1.75 v) lg (threshold 1.75 v) hg (threshold 1.75 v) no failure 1 1 0 1 canl to gnd 0 0 0 1 canh to gnd 0 0 0 0 lb (threshold v sup - 2.0 v) hb (threshold v sup - 2.0 v) lb (threshold v sup - 2.0 v) hb (threshold v sup -2.0 v) no failure 0 0 0 0 canl to vsup 1 1 1 1 canh to vsup 1 1 0 1 l5 (threshold vdd - 0.43 v) h5 (threshold vdd - 0.43 v) l5 (threshold vdd - 0.43 v) h5 (threshold vdd - 0.43 v) no failure 0 0 0 0 canl to vdd 1 1 1 1 canh to vdd 1 1 0 1 hg canh canl lg vdd vrg vrg hb vrvb lb vrvb logic txd diagnostic v dd (5.0 v) gnd (0.0 v) recessive level (2.5 v) v sup (12v?14v) vrvb (v sup - 2.0 v) vrg (1.75 v) canl dominant level (1.4 v) canh dominant level (3.6 v) l5 vr5 h5 vr5 vr5 (v dd - 0.43 v)
analog integrated circuit device data freescale semiconductor 39 33742 functional device operation operational modes detection principle in the recessive state, if one of the two bus lines is shorted to gnd, vdd, or vsup, then voltage at the other line follows the shorted line due to bus termination resistance and the high impedance of the driver. for example, if canl is shorted to gnd, canl voltage is zero, and canh voltage, as measured by the hg comparator, is also close to zero. in the recessive state the fa ilure detection to gnd or vsup is possible. however, it is impossible to distinguish which bus line, canl or canh, is shorted to gnd or vsup. in the dominant state, the complete diagnostic is possible once the driver is turned on. can bus failure reporting canl bus line failures (for example, canl short to gnd) is reported in the spi regist er tim1/2. canh bus line (for example, canh short to vsu p) is reported in the lpc register. in addition can-f and can-uf bits in the can register indicate that a can bus failure has been detected. non-identified and fully identified bus failures as indicated in table 11 , page 38 , when the bus is in a recessive state it is possible to detect an error condition; however, is it not possible to fully identify the specific error. this is called ?non-identified? or ?under-acquisition? bus failure. if there is no communication (i.e., bus idle), it is still possible to warn the mcu that the sbc has started to detect a bus failure. in the can register, bits d2 and d1 (can-f and can-uf, respectively) are used to signal bus failure. bit d2 reports a bus failure and bit d1 indicates if the failure is identified or not (bit d1 is set to logic [1} if the error is not identified). when the detection mechanism is fully operating any bus error will be detected and repor ted in the tim1/2 and lpc registers and bit d1 will be reset to logic [0]. number of samples for proper failure detection the failure detector requir es at least one cycle of recessive and dominant state to properly recognize the bus failure. the error will be fully detected after five cycles of recessive-dominant states. as long as the failure detection circuitry has not detected the sa me error for five recessive- dominant cycles, the bit ?non-identified failure? (can-uf) will be set. rxd permanent recessive failure the purpose of this detection mechanism is to diagnose an external hardware failure at the rxd output pin and to ensure that a permanent failure at the rxd pin does not disturb network communication.in the event rxd is shorted to a permanent high level signal (i.e., 5.0 v), the can protocol module within the mcu cannot receive any incoming message. additionally, the can protocol module cannot distinguish the bus idle state and could start communication at any time. to prevent this, an rxd failure detection, as illustrated in figure 25 and explained below, is necessary. figure 25. rxd path and rxd permanent recessive detection principle canh canl diff vdd rxd sense rxd rxd txd txd 60 ? v1 logic diag canl diff output rxd output rxd short to v1 prop delay rxd flag rxd flag latched 2.0 v sampling sampling sampling sampling note rxd flag is neither the rxpr bi t in the lpc register nor the can - f bit in the intr register. canh driver driver
analog integrated circuit device data 40 freescale semiconductor 33742 functional device operation operational modes rxd failure detection the sbc senses the rxd output voltage at each low-to- high transition of the differentia l receiver. excluding internal propagation delay, rxd output should be low when the differential receiver is low. in the event rxd is shorted to 5.0 v (e.g., to vdd), rxd will be tied to a high level and the rxd short to 5.0 v can be detected at the next low-to-high transition of the differentia l receiver. compete detection requires three samples. when the error is detected, an error flag is latched and the can driver is disabled. the error is reported through the spi register lpc, bit rxpr. recovery condition the sbc will try to recover from a bus fault condition by sampling for a correct low level at txd, as illustrated in figure 26 . as soon as an rxd permanent recessive is detected, the rxd driver is deactivated and a weak pull-down current source is activated in order to allow recovery conditions. the driver stays disabled until the failure is cleared (rxd no longer permanent recessive) and the bus driver is activated by an spi register command (write 1 to the canclr bit in the can register). figure 26. rxd recovery conditions txd permanent dominant failure principle in the event txd is set to a permanent low level, the can bus is set into dominant level, and no communication is possible. the sbc has a txd permanent time-out detector. after time-out, the bus driver is disabled and the bus is released in a recessive state. the txd permanent dominant failure is reported in the tim1 register. recovery the txd permanent dominant is used and activated also in case of txd short to rxd. the recovery condition for txd permanent dominant (recovery means the reactivation of the can drivers) is done by an spi command and is controlled by the mcu. the driver stays disabled until the failure is cleared (txd no longer permanent dominant ) and the bus driver is activated by an spi regist er command (write logic [1] to canclr bit in the can register). txd to rxd short circuit failure principle in the event the txd is shorted to rxd when an incoming can message is received, the rxd will be at a low. consequently, the txd pin is low and drives canh and canl into the dominant state. the bus is stuck in dominant mode and no further communication is possible. detection and recovery the txd permanent dominant timeout will be activated and release the canl and canh drivers. however, at the next incoming dominant bit, the bus will be stuck again in dominant. in order to avoid this situation, the recovery from a failure (recovery means the reactivation of the can drivers) is done by an spi command and controlled by the mcu. internal error output flags there are internal error flags to signal whenever thermal protection is activated or overcurrent detection occurs on the canl or canh pins (therm-cur bit). the errors are reported in the can register. canl diff output rxd output rxd short to v dd rxd flag rxd flag latched sampling sampling note rxd flag is neither the rxpr bit in the lpc register rxd no longer shorted to v dd canh nor the can-f bit in intr register.
analog integrated circuit device data freescale semiconductor 41 33742 functional device operation operational modes device fault operation table 12 describes the relationship between device fault or warning and the operation of the vdd , v2, can, and hs interface . table 12. fault / warning fault / warning vdd v2 can hs battery fail turn off turn off turn off due to v2. no communication off vdd temperature pre-warning warning flag only. leave as is no change no change no change vdd overtemperature turn off turn off turn off due to v2. no communication off vdd overcurrent vdd regulator enters linear mode. vdd undervoltage reset may occurs. vdd overtemperature pre- warning or shutdown may occur turn off if vdd undervoltage reset occurs if v2 is off, turn off and no communication turn off if vdd undervoltage reset occurs vdd short circuit vdd undervoltage reset occurs. vdd overtemperature pre- warning or shutdown may occur turn off turn off due to v2. no communication off watchdog reset on turn off turn off due to v2. no communication off v2low (e.g., v2 < 4.0 v) no change v2 out of range turn off due to v2 low no change hs overtemperature no change no change no change off hs overcurrent no change no change no change hs overtemperature may occur vsup low no change no change no change no change can overtemperature no change no change disable. as soon as temperature falls, can is re-enabled automatically no change can overcurrent no change no change (46) no change canh short to gnd no change no change (47) no communication (48) no change canh short to vdd no change no change communication ok no change canh short to vsup no change no change communication ok no change canl short to gnd no change no change communication ok no change canl short to vdd no change no change no communication (48) no change canl short to vsup no change no change no communication (48) no change notes 46. refer to descriptions of canh and canl shor t to gnd, vdd, and vsup elsewhere in table. 47. peak current 150 ma during txd dominant only. due to loss of communication , can controller reaches bu s off state. average current out of v2 is below 10 ma. 48. overcurrent might be detected. therm-cur bit set in can register.
analog integrated circuit device data 42 freescale semiconductor 33742 functional device operation logic commands and registers logic commands and registers spi interface and register description data format description figure 27 illustrates an 8-bit byte corresponding to the 8 bits in a spi register. the first three bits are used to identify the internal sbc register address. bit 4 is a read/write bit. the last four bits are data sent from the mcu to the sbc or read back from the 33742 to the mcu. the state of the miso has no significance during the write operation. however, during a read operation the final four bits of miso have meaning; namely, they contain the content of the accessed register. figure 27. data format description. register descriptions the following tables in this section describe the spi register list and register bit meaning. register reset values are also described, along with the reset condition. a reset condition is the condition causing the bit to be set at the reset value. bit 7 bit 5 bit 3 bit 4 bit 2 bit 6 bit 1 bit 0 a2 a0 d3 r/w d2 a1 d1 d0 miso mosi address data note read operation: r/w bit = logic [0] write operation: r/w = logic [1] : table 13. possible reset conditions condition name definition 33742 reset por power-on reset 33742 mode transition nr2r normal request to reset mode nr2n normal request to normal mode nr2stb normal request to standby mode n2r normal to reset mode stb2r standby to reset mode sto2r stop to reset mode sto2nr stop to normal request 33742 mode reset 33742s in reset mode table 14. list of registers register address formal name and link comment and use write read mcr $000 mode control register (mcr) on page 43 selection for normal, standby, sleep, stop, and debug modes batfail, general failure, vdd pre- warning, and watchdog flag rcr $001 reset control register (rcr) on page 44 configuration for reset voltage level, can sleep and stop modes can $010 can register (can) on page 44 can slew rate, sleep and wake-up enable/disable modes, drive enable after failure can wake-up and can failure status bits ior $011 input / output register (ior) on page 45 hs (high-side switch) control in normal and standby mode hs overtemperature bit, vsup, and v2 low status wur $100 on page 46 control of wake-up input polarity wake-up input and real time lx input state tim $101 timing register (tim1 / 2) on page 47 ? tim1: watchdog timing control, watch - dog window (wdw) or watchdog tim - eout (wto) mode ? tim2: cyclic sense and forced wake- up timing selection canl and txd failure reporting lpc $110 low power control register (lpc) on page 49 control hs periodic activation in sleep and stop modes, forced wake-up mode activation, can-int mode selection canh and rxd failure reporting intr $111 interrupt register (intr) on page 51 enable or disable of interrupts interrupt source
analog integrated circuit device data freescale semiconductor 43 33742 functional device operation logic commands and registers mode control register (mcr) tables 15 through 17 describes the various mode control registers. table 15. mode control register mcr r/w d3 d2 d1 d0 $000b w ? mctr2 mctr1 mctr0 r batfail (49) vddtemp gfail wdrst reset value ? ? 0 0 0 reset condition (write) (50) ? ? por, reset por, reset por, reset notes 49. batfail bit cannot be set by spi. batfa il is set when vsup falls below 3.0 v. 50. see table 13 page 42 , for definitions of reset conditions table 16. mode control register control bits mctr 2 mctr 1 mctr 0 33742s mode description 0 0 0 enter/exit debug mode to enter/exit debug mode, refer to detailed description in debug mode: hardware and software debug with the 33742 , page 30 . 0 0 1 normal ? 0 1 0 standby ? 0 1 1 stop, watchdog off (51) ? 0 1 1 stop, watchdog on (51) ? 1 0 0 sleep (52) ? 1 0 1 normal no watchdog running. debug mode. 1 1 0 standby 1 1 1 stop notes 51. watchdog on or off depends on rcr bit d3. 52. before entering sleep mode, batfail bit in mcr must be previ ously cleared (mcr read operation), and nostop bit in rcr must b e previously set to logic [1]. table 17. mode control register status bits name logic description batfail 0 vsup was not below v bf . 1 vsup has been below v bf . vddtemp 0 no overtemperature pre-warning. 1 temperature pre-warning on vdd regulator (bit latched). gfail 0 no failure. 1 can failure or hs overtemperature or v2 low. wdrst 0 no watchdog reset occurred. 1 watchdog reset occurred.
analog integrated circuit device data 44 freescale semiconductor 33742 functional device operation logic commands and registers reset control register (rcr) tables 18 and 19 contain various reset control register information. can register (can) tables 20 through 23 contain the information on the can register . table 20 describes control of the high-speed can module, mode, slew rate, and wake-up. table 18. reset control register rcr r/w d3 d2 d1 d0 $001b w wdstop nostop can sleep rstth r reset value ? 1 0 0 0 reset condition (write) (53) ? por, reset, sto2nr por, nr2n, nr2stb por, nr2n, nr2stb por notes 53. see table 13 page 42 , for definitions of reset conditions. table 19. reset control register control bits name logic description wdstop 0 no watchdog in stop mode. 1 watchdog runs in stop mode. nostop 0 device cannot enter sleep mode. 1 sleep mode allowed. device can enter sleep mode. can sleep 0 can sleep mode disable (despite d0 bit in can register). 1 can sleep mode enabled (in addition to d0 in can register). rstth 0 reset threshold 1 selected (typ 4.6 v). 1 reset threshold 2 selected (typ 4.2 v). table 20. can register can r/w d3 d2 d1 d0 $010b w canclr sc1 sc0 mode r canwu can-f can-uf therm-cur reset value ? 0 0 0 1 reset condition (write) (54) ? por por por nr2n, stb2n notes 54. see table 13 , page 42 , for definitions of reset conditions. table 21. canclr control bits logic description 0 no effect. 1 re-enables can driver after txd permanent dominant or rxd permanent recessive failure occurred. failure recovery conditions must occur to re-enable.
analog integrated circuit device data freescale semiconductor 45 33742 functional device operation logic commands and registers high-speed can transceiver modes the mode bit (d0) controls the state of the can interface, txrx or sleep mode ( table 22 ). sc0 bit (d1) defines the slew rate when the can module is in txrx, and it controls the wake-up option (wake-up enable or disable) when the can module is in sleep mode. input / output register (ior) tables 24 through 26 contain the input / output register information. table 25 provides information about information hs control in normal and standby modes, while table 26 provides status bit information. table 22. can high-speed transceiver modes sc1 sc0 mode can mode (pass 1.1) 0 0 0 can txrx, slew rate 0 0 1 0 can txrx, slew rate 1 1 0 0 can txrx, slew rate 2 1 1 0 can txrx, slew rate 3 x 1 1 can sleep and can wake-up disable x 0 1 can sleep and can wake-up enable x = don?t care. table 23. can register status bits name logic description canwu 0 no can wake-up occurred. 1 can wake-up occurred. can-f 0 no can failure. 1 can failure (55) . can-uf 0 identified can failure (55) . 1 non-identified can failure. therm-cur 0 no overtemperature or overcurrent on canh or canl drivers. 1 overtemperature or overcurrent on canh or canl drivers. notes 55. error bits are latched in the can register. table 24. input / output register ior r/w d3 d2 d1 d0 $011b w ? hson ? ? r v2low hsot vsuplow debug reset value ? ? 0 ? ? reset condition (write) (56) ? ? por ? ? notes 56. see table 13 , page 42 , for definitions of reset conditions.
analog integrated circuit device data 46 freescale semiconductor 33742 functional device operation logic commands and registers wake-up register (wur) tables 27 through 29 contain the wake-up register information. local wake-up inputs l0 : l3 can be used in both normal and standby modes as port expander, as well as for waking up the sbc from sleep or stop modes ( table 27 ). wake-up inputs can be configured by pair. l0 and l1 can be configured together, and l1 and l2, and l2 and l3 can be configured together ( table 28 ). table 25. hson control bits logic hs state 0 hs off, in normal and standby modes. 1 hs on, in normal and standby modes. (57) . notes 57. when hs is turned off due to an overtemperature condition, it can be turned on again by setting the appropriate control bit to 1. error bits are latched in the ior register. table 26. input / output register status bits name logic description v2low 0 v 2lth > 4.0 v. 1 v 2lth < 4.0 v. hsot 0 no hs overtemperature. 1 hs overtemperature. vsuplow 0 v bf(ew) > 5.8 v. 1 v bf(ew) < 5.8 v. debug 0 sbc not in debug mode. 1 sbc accepts command to go to debug modes (no watchdog). table 27. wake-up register wur r/w d3 d2 d1 d0 $100b w lctr3 lctr2 lctr1 lctr0 r l3wu l2wu l1wu l0wu reset value ? 0 0 0 0 reset condition (write) (58) ? por, nr2r, n2r, stb2r, sto2r notes 58. see table 13 , page 42 , for definitions of reset conditions.
analog integrated circuit device data freescale semiconductor 47 33742 functional device operation logic commands and registers timing register (tim1 / 2) tables 30 through 34 contain the timing register information. the tim register is compos ed of two sub registers: ?tim1 ? controls the watchdog timing selection as well as either the watchdog window or the watchdog time-out option ( figure 28 and figure 29 , respectively). tim1 is selected when bit d3 is 0 ( table 30 ). watchdog timing characteristics are described in table 31 . ?tim2 ? selects an appropriate timing for sensing the wake-up circuitr y or cyclically supplying devices by switching the hs on or off. tim2 is selected when bit d3 is 1 ( table 32 ). figure 30 , page 49 , describes hs operation when cyclic sense is selected cyclic sense timing characteristics are described in table 34 , page 49 . both subregisters also report the canl and txd diagnostics. table 28. wake-up register control bits lctr3 lctr2 lctr1 lctr0 l0 l1 : l1 l2 config l2 l3 : l3 l4 config x x 0 0 inputs disabled ? x x 0 1 high level sensitive x x 1 0 low level sensitive x x 1 1 both level sensitive 0 0 x x ? inputs disabled 0 1 x x high level sensitive 1 0 x x low level sensitive 1 1 x x both level sensitive x = don?t care. table 29. wake-up register status bits (59) name logic description l 3 wu 0 or 1 if bit = 1, wake-up occurred from sleep or stop modes; if bit = 0, no wake-up has occurred. when device is in normal or standby m ode, bit reports the state on lx pin (low or high) (0 = lx low, 1 = lx high) l2wu 0 or 1 l1wu 0 or 1 l0wu 0 or 1 notes 59. wur status bits have two functions. after sbc wake-up, they indicate the wake up source; for example, l2wu set at logic [1] if wake- up source is l2 input. after sbc wake-up and once the wur register has been read, status bits indicate the real-time state of the lx inputs (1 = lx is above threshold, 0 = lx input is below threshold). if after a wake- up from lx input a watchdog tomato occurs before the first reading of the wur register, the lxwu bits are re set. this can occur only if the sbc was in stop mode. table 30. tim1 timing and canl failure diagnostic register tim1 r/w d3 d2 d1 d0 $101b w 0 wdw wdt1 wdt0 r canl2vdd canl2bat canl2gnd txpd reset value ? ? 0 0 0 reset condition (write) (60) ? ? por, reset por, reset por, reset notes 60. see table 13 , page 42 , for definitions of reset conditions.
analog integrated circuit device data 48 freescale semiconductor 33742 functional device operation logic commands and registers figure 28. window watchdog figure 29. timeout watchdog table 31. tim1 control bits wdw wdt1 wdt0 timing (ms typ) parameter description 0 0 0 9.75 watchdog period 1 no window watchdog 0 0 1 45 watchdog period 2 0 1 0 100 watchdog period 3 0 1 1 350 watchdog period 4 1 0 0 9.75 watchdog period 1 watchdog window enabled (window length is half the watchdog timing). 1 0 1 45 watchdog period 2 1 1 0 100 watchdog period 3 1 1 1 350 watchdog period 4 watchdog timing x 50% watchdog timing x 50% watchdog period (watchdog timing selected by tim1 bit wdw =1) window closed no watchdog clear allowed window open for watchdog clear watchdog period (watchdog timing selected by tim1 bit wdw = 0) window open for watchdog clear table 32. timing register status bits name logic failure description canl2vdd 0 no canl short to vdd. 1 canl short to vdd. canl2bat 0 no canl short to vsup . 1 canl short to vsup . canl2gnd 0 no canl short to gnd. 1 canl short to gnd. txpd 0 no txd dominant. 1 txd dominant. table 33. tim2 timing and canl failure diagnostic register tim2 r/w d3 d2 d1 d0 $101b w 1 csp2 csp1 csp0 r canl2vdd canl2bat canl2gnd txpd reset value ? ? 0 0 0 reset condition (write) (61) ? ? por, reset por, reset por, reset notes 61. see table 13 , page 42 , for definitions of reset conditions.
analog integrated circuit device data freescale semiconductor 49 33742 functional device operation logic commands and registers figure 30. hs operation when cyclic sense is selected low power control register (lpc) tables 35 through 39 contain the low power control register information. the lpc register controls: ? the state of hs in stop and sleep mo des (hs permanently off or hs cyclic). ? enable or disable of the forced wake-up function (sbc automatic wake-up after time spent in sleep or stop modes; time is defined by the tim2 sub register). ? enable or disable the sense of the wake-up inputs (lx) at the sampling point of the cyclic sense period (lx2hs bit). (refer to reset control register (rcr) on page 44 for details of the lpc register setup requ ired for proper cyclic sense or direct wake- up operation. the lpc register also reports the canh and rxd diagnostic. cyclic sense timing, off time time hs sample 10 s hs off hs on lx sampling point cyclic sense timing, on time table 34. tim2 control bits csp2 csp1 csp0 cyclic sense timing (ms) parameter 0 0 0 4.6 cyclic sense/fwu timing 1 0 0 1 9.25 cyclic sense/fwu timing 2 0 1 0 18.5 cyclic sense/fwu timing 3 0 1 1 37 cyclic sense/fwu timing 4 1 0 0 74 cyclic sense/fwu timing 5 1 0 1 95.5 cyclic sense/fwu timing 6 1 1 0 191 cyclic sense/fwu timing 7 1 1 1 388 cyclic sense/fwu timing 8 table 35. low power control register lpc r/w d3 d2 d1 d0 $110b w lx2hs fwu can-int hsauto r canh2vdd canh2bat canh2gnd rxpr reset value ? 0 0 0 0 reset condition (write) (62) ? por, nr2r, n2r, stb2r, sto2r por, nr2r, n2r, stb2r, sto2r por, nr2r, n2r, stb2r, sto2r por, nr2r, n2r, stb2r, sto2r notes 62. see table 13 , page 42 , for definitions of reset conditions.
analog integrated circuit device data 50 freescale semiconductor 33742 functional device operation logic commands and registers table 36. lx2hs control bits logic wake-up inputs supplied by hs 0 no. 1 yes. lx inputs sensed at sampling point. table 37. hsauto control bits logic auto-timing hs in sleep and stop modes 0 off. 1 on, hs cyclic, period defin ed in tim2 subregister. table 38. can-int control bits logic (63) description 0 interrupt as soon as can bus failure detected. 1 interrupt when can bus failure detected and fully identified. notes 63. if can-int is at logic [0], any undetermined can failure will be latched in the can register (bit d1: can-uf) and can be accessed by spi (refer to can register (can) on page 44 ). after reading the can register or setting can-int to logic [1], it will be cleared automatically. the existence of can-uf al ways has priority over clearing, meaning that a further undetermined can failure does not allow clearing the can-uf bit. table 39. lpc status bits name logic failure description canh2vdd 0 no canh short to vdd. 1 canh short to vdd. canh2bat 0 no canh short to vsup. 1 canh short to vsup. canh2gnd 0 no canh short to gnd. 1 canh short to gnd. rxpr 0 no rxd permanent recessive. 1 rxd permanent recessive.
analog integrated circuit device data freescale semiconductor 51 33742 functional device operation logic commands and registers interrupt register (intr) tables 40 through 42 contain the interrupt register information. the intr register allows masking or enabling the interrupt source. a read operation identifies the interrupt source. table 42 provides status bit information. the status bits of the intr register content are c opies of the ior, can, tim, and lpc registers status content. to clear the interrupt register bits, the i or, can, tim, and/or lpc registers must be cl eared (read register) and the recovery condi tion must occur. errors bits are latched in the can register and the ior register. when the mask bit is set, the int pin goes low if the appropriate condition occurs. upon a wake-up condition from stop mode due to overcurrent detection (i dds-wu1 or i dds-wu2 ), an int pulse is generated; however, intr register content remains at 0000 (not bit set into the intr register). table 40. interrupt register intr r/w d3 d2 d1 d0 $111b w vsuplow hsot-v2low (64) v1temp canf r vsuplow hsot v1temp canf reset value ? 0 0 0 0 reset condition (write) (65) ? por, rst por, rst por, rst por, rst notes 64. if only hsot - v2low interrupt is selected (only bit d2 set in intr registe r), reading intr register bit d2 leads to two possibilities: 1. bit d2 = 1: interrupt source is hsot. 2. bit d2 = 0: interrupt source is v2low. hsot and v2low bits status are available in the ior register. 65. see table 13 , page 42 , for definitions of reset conditions. table 41. interrupt register control bits name description canf mask bit for can failures. vddtemp mask bit for vdd medium temperature (pre-warning). hsot - v2low mask bit for hs overtemperature and v 2lth < 4.0 v. vsuplow mask bit for v bf(ew) < 5.8 v. table 42. interrupt register status bits name logic description vsuplow 0 no v bf(ew) < 5.8 v. 1 v bf(ew) < 5.8 v. hsot 0 no hs overtemperature. 1 hs overtemperature. vddtemp 0 no vdd medium temperature (pre-warning). 1 vdd medium temperature (pre-warning). canf 0 no can failure. 1 can failure.
analog integrated circuit device data 52 freescale semiconductor 33742 typical applications typical applications sbc power supply the 33742 is supplied from the battery line. a serial diode is necessary to protect the devic e against negative transient pulse s and from reverse battery. this is illustrated in figure 31 . figure 31. sbc typical application schematic programmable spi interface dual voltage regulator gnd rxd txd vsup monitor vdd monitor hs mode control reset watchdog wake-up input 1.0 mbps can physical interface cs miso sclk mosi rst int 5.0 v/200 ma v2ctrl vdd l0 hs canl canh oscillator v2 v2 wdog v sup l1 l2 l3 control interrupt v pwr q1 c3 c4 c2 c1 c6 to l1 r1 c8 to l2 r3 mcu safe circuitry d1 c5 rp rp rd c7 to l1 r2 c9 to l3 r4 rd internal connector clamp (1) sw4 sw3 sw2 sw1 c10 module supply legend d1: example: 1n4002 type q1: mjd32c r1, r2, r3, r4: 10 k ? rp, rd: example: 1.0 k ? depending on switch type. r5: 2.2 k ? c1: 10 f c2: 100 nf c3: 47 f c4: 100 nf c5: 47 f tantalum or 100 f chemical c6, c7, c8, c9, c10: 100 nf (1) clamp circuit to ensure ma x ratings for hs (hs from - 0.3 v to v sup + 0.3) are respected. r5 33742
analog integrated circuit device data freescale semiconductor 53 33742 typical applications voltage regulator the sbc contains two 5.0 v regulators: a v1 regulator, fully integrated and protected, and a v2 regulator, which operates with an external ballast transistor. vdd regulator the vdd regulator provides 5.0 v output, 2.0% accuracy with current capability of 200 ma max. it requires external decoupling and stabilizing capacitors. the minimum recommended values are as follows: ? c4: 100 nf ? c3: 10 f < c3 <22 f, esr < 1.0 ? or ? c3: 22 f < c3 <47 f, esr < 5.0 ? or ?c3: 47 f, esr < 10 ? v2 regulator: oper ating with external ballast transistor the v2 regulator is a tracking regulator of the vdd output. its accuracy relative to vdd is 1.0%. it requires external decoupling and stabilizing capacitors. the recommended value are as follows: ?22 f, esr < 5.0 ? ?47 f, esr < 10 ? the v2 pin has two functions: it is a sense input for the v2 regulator and is a 5.0 v power supply input to the can interface. with respect to ballast transis tor selection, either pnp or pmos transistors may be used. a resistor between base and emitter (or source and drain) is necessary to ensure proper operation and optimized performances. recommended bipolar transistor is mjd32c. v2 regulator: operation without ballast transistor the external ballast transistor is optional. if the application does not requires more than the maximum output current capability of the vdd regulator, then the ballast transistor can be omitted. the thermal aspects must be analyzed as well. the electrical connection is illustrated in figure 32 . figure 32. v2 regulator electrical connection failure on vdd, wdog, reset, and int pins the paragraphs below describe the behavior of the device and of the int , rst , and wdog pins at power-up and under failure of the vdd regulator. power-up and sbc entering normal operation after power-up the 33742 enters normal request mode (can interface is in txrx mode): vdd is on and v2 is off. after 350 ms if no watchdog is written (no tim1 register write), a reset occurs and the 33742 returns to normal request mode. during this sequence wdog is active (low level). once watchdog is written, the 33742 goes to normal mode: vdd is still on and v2 turns on, wdog is no longer active, and the rst pin is high. if watchdog is not refreshed, the 33742 generates a reset and returns to normal request mode. figure 33 , page 54 , illustrates the operation. vdd vsup v2ctrl rst c3 c4 c1 c2 v dd reset 33742 v2 no connect components list c1: 22 f c2: 100 nf c3: >10 f c4: 100 nf mcu v pwr
analog integrated circuit device data 54 freescale semiconductor 33742 typical applications figure 33. power up sequence, no w/d write at first power up and vdd going low with stop mode as default low power mode is selected the first part of figure 34 is identical to figure 33 . if vdd is pulled below vdd undervoltage reset (typ 4.6 v), say by an overcurrent or short circuit (for instance, short to 4.0 v), and if a low power mode previously selected was stop mode, the 33742 enters reset mode ( rst pin is active). the wdog pin stays high, but the high level (voh) follows v1 level. the int pin goes low. when the vdd overload condition is removed, the 33742 restarts in normal request mode. figure 34. undervoltage on vdd vdd spi (cs) int wd rst missing watchdog refresh sbc in reset mode sbc in normal request & reset modes sbc in normal mode sbc in normal request & reset modes watchdog refresh reset each 350 ms 350 ms watchdog refresh vdd spi (cs) int wd rst missing watchdog refresh sbc in reset mode sbc in normal request & reset modes sbc in normal mode sbc in normal request & reset modes watchdog refresh reset each 350 ms 350 ms watchdog refresh sbc in normal request & reset modes sbc in normal mode sbc in reset mode watchdog refresh reset each 350 ms 350 ms vdd sbc in reset mode under voltage at vdd (vdd < v rstth ) spi (cs) int wd rst sbc in normal request & reset modes sbc in normal mode sbc in reset mode watchdog refresh reset each 350 ms 350 ms vdd sbc in reset mode under voltage at vdd (vdd < v rstth ) spi (cs) int wd rst
analog integrated circuit device data freescale semiconductor 55 33742 typical applications power-up and vdd going low with sleep mode as default low power mode is selected the first part of figure 35 is identical to figure 34 . if vdd is pulled below the vdd under voltage reset (typ 4.6v), say by an overcurrent or short circuit (for instance, short to 4.0 v), and if the low power mode previously selected was sleep mode and if the batfail flag has been cleared, the 33742 ente rs in reset mode for a time period of 100 ms. the wdog pin stays high, but the high level (voh) follows vdd level. the rst and int pins are low. after 100 ms the 33742 goes into sleep mode, and the vdd and v2 are off. figure 35 shows an example wherein vdd is shorted to 4.0 v, and after 100 ms the 33742 enters sleep mode. . figure 35. undervoltage at vdd. sleep mode selected. figure 36. can bus standard termination figure 37. can bus split termination sbc in reset mode for 100ms, then enter sleep mode sbc in sleep mode 100 ms sbc in normal request & reset modes sbc in normal mode reset each 350 ms vdd sbc in reset mode watchdog refresh under voltage at vdd spi (cs) int wd rst sbc in reset mode for 100ms, then enter sleep mode sbc in sleep mode 100 ms sbc in normal request & reset modes sbc in normal mode reset each 350 ms vdd sbc in reset mode watchdog refresh under voltage at vdd spi (cs) int wd rst r5 cl canl (33742) ch canh (33742) can connector canl canh legend r5: 60 ? cl, ch: 220 pf r6 cl canl (33742) ch canh (33742) can connector r7 cs canh canl legend r6, r7: 30 ? cl, ch: 220 pf cs: > 470 pf
analog integrated circuit device data 56 freescale semiconductor 33742 packaging package and thermal considerations packaging package and thermal considerations the 33742 sbc is a standard surface mount 28-pin soic wide bod y. in order to improve the thermal performances of the soic package, eight of the 28 pins are internally connected to the package lead frame for heat transfer to the printed circuit board. packaging dimensions important for the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98a drawing number below. dw suffix eg suffix (pb-free) 28-lead soicw plastic package 98asb42345b issue g
analog integrated circuit device data freescale semiconductor 57 33742 packaging packaging dimensions dw suffix eg suffix (pb-free) 28-lead soicw plastic package 98asb42345b issue g
analog integrated circuit device data 58 freescale semiconductor 33742 packaging packaging dimensions ep suffix (pb-free) 48-lead qfn 98arh99048a issue f
analog integrated circuit device data freescale semiconductor 59 33742 packaging packaging dimensions ep suffix (pb-free) 48-lead qfn 98arh99048a issue f
analog integrated circuit device data 60 freescale semiconductor 33742 packaging packaging dimensions ep suffix (pb-free) 48-lead qfn 98arh99048a issue f
analog integrated circuit device data freescale semiconductor 61 33742 additional documentation thermal addendum (rev 2.0) additional documentation thermal addendum (rev 2.0) introduction this thermal addendum is provid ed as a supplement to the mc33742 technical datasheet. the addendum provides thermal performance information that ma y be critical in the desig n and development of system applications. all electrical, application, and packaging information is provided in the data sheet. packaging and thermal considerations the mc33742 is offered in a 28 pin soicw exposed pad, single die package. there is a single heat source (p), a single junction temperature (t j ), and thermal resistance (r ja ). the stated values are solely for a thermal performance comparison of one package to another in a standardi zed environment. this methodology is not meant to and will not predict the performance of a package in an application-specific environment. stated values were obtained by measurement and simulation according to the standards listed below. standards figure 38. surface mount for soic wide body non-exposed pad 28-pin soicw 33742dw dw suffix eg suffix (pb-free) 98asb42345b 28-pin soicw note for package dimensions, refer to the 33742 data sheet. 33742eg t j = r ja . p table 43. thermal performance comparison thermal resistance [ c/w] r ja (1) (2) 41 r jb (2) (3) 10 r ja (1) (4) 68 r jc (5) 220 notes: 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-7. 3. per jedec jesd51-8, with the board temperature on the center trace near the center lead. 4. single layer thermal test board per jedec jesd51-3. 5. thermal resistance between the die junction and the package top surface; cold plate attached to the package top surface and remaining surfaces insulated. 1.0 1.0 0.2 0.2 * all measurements are in millimeters 28 pin soicw 1.27 mm pitch 16.0 mm x 7.5 mm body
analog integrated circuit device data 62 freescale semiconductor 33742 additional documentation thermal addendum (rev 2.0) figure 39. thermal test board device on thermal test board table 44. thermal resistance performance r ja is the thermal resistance between die junction and ambient air . wdog miso sclk gnd gnd gnd gnd canl canh l3 l2 l1 cs mosi rxd rst int gnd gnd gnd gnd v2 v2ctrl vsup hs l0 txd vdd 4 5 6 7 8 9 10 11 12 13 14 2 3 28 25 24 23 22 21 20 19 18 17 16 15 27 26 1 33742 pin connections 28-pin soicw 1.27 mm pitch 18.0 mm x 7.5 mm body a material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a : cu heat-spreading areas on board surface ambient conditions: natural convection, still air a [mm2] r ja [c/w] 0 68 300 52 600 47
analog integrated circuit device data freescale semiconductor 63 33742 additional documentation thermal addendum (rev 2.0) figure 40. device on thermal test board r ja figure 41. transient thermal resistance r j a , 1 w step response, device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 70 80 heat spreading area a [mm2] thermal resistance [oc/w ] 0 300 600 r ja x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time[s] thermal resistance [oc/w] r ja x
analog integrated circuit device data 64 freescale semiconductor 33742 revision history revision history revision date description of changes 3.0 2/2006 ? converted to freescale format ? implemented revision history page 4.0 6/2006 ? added thermal addendum (rev. 1.0) ? changed data sheet from ?advanced? to ?final? 5.0 8/2006 ? added MCZ33742eg/r2 and MCZ33742seg/r2 to the ordering information block 6.0 8/2006 ? replaced label for logic inputs to logic signals (rxd, txd, mosi, miso, cs, sclk, rst, wdog, and int) on page 7 7.0 10/2006 ? removed all references to the 54 pin package. ? removed peak package reflow temperature duri ng reflow (solder reflow) parameter from maximum ratings on page 7 . added note with instructions from www.freescale.com. 8.0 2/2007 ? restated notes in maximum ratings on page 7 9.0 3/2007 ? text corrections to the included thermal addendum 10.0 5/2007 ? added 48 pin qfn package, part number pcz33742ep/r2, and outline package drawing number 98arh99048a.
mc33742 rev. 10.0 5/2007 rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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